Altera IP Compiler for PCI Express - Manual (Page 40)

3–4 Chapter 3: Parameter Settings
Parameters in the Qsys Design Flow
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Link Capabilities
Table 3–4 describes the capabilities parameter available in the Link Capabilities
section of the IP Compiler for PCI Express parameter editor in the Qsys design flow.
Error Reporting
The parameters in the Error Reporting section control settings in the PCI Express
advanced error reporting extended capability structure, at byte offsets
0x800 through
0x834 . Table 3–5 describes the error reporting parameters available in the Qsys design
flow.
Subsystem ID
0x02C
0x0004 Sets the read-only value of the subsystem device ID register.
Subsystem vendor ID
0x02C
0x1172
Sets the read-only value of the subsystem vendor ID register. This
parameter can not be set to 0xFFFF per the
PCI Express Base
Specification 1.1 or 2.0 .
Table 3–3. PCI Registers (Part 2 of 2)
Table 3–4. Link Capabilities Parameter
Parameter Value Description
Link port number 1
Sets the read-only value of the port number field in the link
capabilities register. (offset
0x08C in the PCI Express capability
structure or PCI Express Capability List register).
Table 3–5. Error Reporting Capabilities Parameters
Parameter Value Description
Implement
advanced error
reporting
On/Off Implements the advanced error reporting (AER) capability.
Implement ECRC
check
On/Off
Enables ECRC checking capability. Sets the read-only value of the ECRC check
capable bit in the advanced error capabilities and control register. This parameter
requires you to implement the advanced error reporting capability.
Implement ECRC
generation
On/Off
Enables ECRC generation capability. Sets the read-only value of the ECRC generation
capable bit in the advanced error capabilities and control register. This parameter
requires you to implement the advanced error reporting capability.