Altera IP Compiler for PCI Express - Manual (Page 150)

6–2 Chapter 6: Register Descriptions
Configuration Space Register Content
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Table 6–2 describes the type 0 configuration settings.
1 In the following tables, the names of fields that are defined by parameters in the
parameter editor are links to the description of that parameter. These links appear as
green text.
0x2C0:0x2FC Port VC3 arbitration table (Reserved)
0x300:0x33C Port VC4 arbitration table (Reserved)
0x340:0x37C Port VC5 arbitration table (Reserved)
0x380:0x3BC Port VC6 arbitration table (Reserved)
0x3C0:0x3FC Port VC7 arbitration table (Reserved)
0x400:0x7FC Reserved
0x800:0x834 Implement advanced error reporting (optional)
0x838:0xFFF Reserved
Table 6–1. Common Configuration Space Header (Part 2 of 2)
Byte Offset 31:24 23:16 15:8 7:0
Table 6–2. PCI Type 0 Configuration Space Header (Endpoints), Rev2 Spec: Type 0 Configuration Space Header
Byte Offset 31:24 23:16 15:8 7:0
0x000 Device ID Vendor ID
0x004 Status Command
0x008 Class code Revision ID
0x00C 0x00
Header Type
( Port type )
0x00 Cache Line Size
0x010 BAR Table (BAR0)
0x014 BAR Table (BAR1)
0x018 BAR Table (BAR2)
0x01C BAR Table (BAR3)
0x020 BAR Table (BAR4)
0x024 BAR Table (BAR5)
0x028 Reserved
0x02C Subsystem ID Subsystem vendor ID
0x030 Expansion ROM base address
0x034 Reserved Capabilities Pointer
0x038 Reserved
0x03C 0x00 0x00 Interrupt Pin Interrupt Line
Note to Table 6–2 :
(1) Refer to Table 6–23 on page 6–12 for a comprehensive list of correspondences between the configuration space registers and the PCI Express
Base Specification 2.0.