Altera IP Compiler for PCI Express - Manual (Page 335)

Chapter : B–17
Descriptor/Data Interface
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Transaction Examples Using Transmit Signals
This section provides the following examples that illustrate how transaction signals
interact:
■ Ideal Case Transmission
■ Transaction Layer Not Ready to Accept Packet
■ Possible Wait State Insertion
■ Transmit Request Can Remain Asserted Between Transaction Layer Packets
■ Priority Given Elsewhere
■ Transmit Request Can Remain Asserted Between Transaction Layer Packets
■ Multiple Wait States Throttle Data Transmission
■ Error Asserted and Transmission Is Nullified
Ideal Case Transmission
In the ideal case, the descriptor and data transfer are independent of each other, and
can even happen simultaneously. Refer to
Figure B–12 . The IP core transmits a
completion transaction of eight dwords. Address bit 2 is set to 0.
In clock cycle 4, the first data phase is acknowledged at the same time as transfer of
the descriptor.
Figure B–12. TX 64-Bit Completion with Data Transaction of Eight DWORD Waveform
clk
tx_req
tx_ack
tx_desc[127:0]
tx_dfr
tx_dv
tx_data[63:32]
tx_data[31:0]
tx_ws
tx_err
CPLD
DW0
DW1
DW2
DW3
DW4
DW5
DW6
DW7
1 2 3 4 5 6 7 8 9
Descriptor
Signals
Data
Signals