Altera IP Compiler for PCI Express - Manual (Page 362)

Info–2 Chapter :
Revision History
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
May 2011 11.0
■ Changed IP core name to IP Compiler for PCI Express.
■ Removed support for Stratix V devices.
■ Added Qsys support.
■ Added Chapter 16, Qsys Design Example .
■ Corrected Table 1–9 on page 1–12 to indicate that IP Compiler for PCI Express variations
that include an Avalon-MM interface cannot target a Cyclone II, Cyclone III, Stratix II, or
Stratix III device.
■ Changed clocking description for PIPE mode in “Clocking for a Generic PIPE PHY and the
Simulation Testbench” on page 7–11 . Fixed section hierarchy.
■ Addded Correctable and Uncorrectable status register descriptions in Chapter 12, Error
Handling .
■ Described the sequence to enable the reverse parallel loopback path in Chapter 17,
Debugging .
■ Updated description of criteria for unsupported request completion status in Table 12–4 on
page 12–3 .
■ Fixed clocking figure Figure 7–4 on page 7–5 (previously Figure 7-6).
■ Updated definition of rx_st_mask in Table 5–2 on page 5–6 .
■ Added definition for test_in[7] signal and aligned expected input values for test_in[3]
and test_in[11:8] with design example, in
Table 5–32 on page 5–58 .
■ Corrected title for Figure 7–6 . This figure also applies to Cyclone IV GX ×1 and does not
apply to ×8.
■ Updated Table 4–1 on page 4–5 to clarify the variations that support a 62.5 MHz applicatin
clock.
■ Corrected Table 4–1 on page 4–5 which showed support for Gen2 in Arria II GX. Arria II GX
does not support Gen2. Arria II GZ supports Gen2.
■ Clarified definition of rx_st_err signal in Table 5–2 on page 5–6 . ECC checking is always
on for hard IP variants with the exception of Gen2 ×8.
■ Added 0x1A speed.recovery state in definition of ltssm in Table 5–7 on page 5–24 .
■ Fixed definition of tl_cfg_sts[0] in Table 5–13 on page 5–30 .
Date Version Changes Made SPR