Altera IP Compiler for PCI Express - Manual (Page 89)

Chapter 5: IP Core Interfaces 5–3
Avalon-ST Interface
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Figure 5–2. Signals in the Hard IP Implementation Endpoint with Avalon-ST Interface
Notes to Figure 5–2 :
(1) Available in Stratix IV GX, devices. For Stratix IV GX devices, = 16 for ×1 and ×4 IP cores and = 33 in the ×8 IP core.
(2) Available in Stratix IV GX. For Stratix IV GX reconfig_togxb, = 3.
rx_st_ready
rx_st_valid
rx_st_data [63:0], [127:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_err
rx_st_mask
rx_st_bardec [7:0]
rx_st_be [7:0], [15:0]
IP Compiler for PCI Express Hard IP Implementation
Test
Interface
Rx Port
(Path to
Virtual
Channel )
tx_st_ready
tx_st_valid
tx_st_data [63:0], [127:0]
tx_st_sop
tx_st_eop
tx_st_empty
tx_st_err
tx_fifo_full
tx_fifo_empty
tx_fifo_rdptr [3:0]
tx_fifo_wrptr [3:0]
tx_cred [35:0]
nph_alloc_1cred_vc0
npd_alloc_1cred_vc0
npd_cred_vio_vc0
nph_cred_vio_vc0
Interrupt
Power
Mnmt
Completion
Interface
Clocks -
Simulation
Only
Tx Port
(Path to
Virtual
Channel )
Config
LMI
(1)
(2)
lmi_dout[31:0]
lmi_ack
lmi_addr[11:0]
lmi_din[31:0]
lmi_rden
lmi_wren
pipe_mode
rate_ext
txdata0_ext[7:0]
txdatak0_ext
txdetectrx0_ext
txelecidle0_ext
txcompl0_ext
rxpolarity0_ext
powerdown0_ext[1:0]
tx_pipemargin
tx_pipedeemph
rxdata0_ext[7:0]
rxdatak0_ext
rxvalid0_ext
phystatus0_ext
rxelecidle0_ext
rxstatus0_ext[2:0]
pipe_rstn
pipe_txclk
8-bit
PIPE PIPE
Interface
Simulation
Only (4)
test_out[63:0]
test_in[39:0]
lane_act[3:0]
rx_st_fifo_full
rx_st_fifo_empty
tl_cfg_add[3:0]
tl_cfg_ctl[31:0]
tl_cfg_ctl_wr
tl_cfg_sts[52:0]
tl_cfg_sts_wr
hpg_ctrler
pclk_in
clk250_out
clk500_out
reconfig_fromgxb[ :0]
reconfig_togxb[ :0]
reconfig_clk
cal_blk_clk
fixedclk_serdes
busy_altgxb_reconfig
pll_powerdown
gxb_powerdown
for
internal
PHY
tx_out0
tx_out1
tx_out2
tx_out3
tx_out4
tx_out5
tx_out6
tx_out7
rx_in0
rx_in1
rx_in2
rx_in3
rx_in4
rx_in5
rx_in6
rx_in7
Serial
IF to
PIPE
Avalon-ST
Avalon-ST
Component
Specific
Component
Specific
ECC Error
avs_pcie_reconfig_address[7:0]
avs_pcie_reconfig_byteenable[1:0]
avs_pcie_reconfig_chipselect
avs_pcie_reconfig_write
avs_pcie_reconfig_writedata[15:0]
avs_pcie_reconfig_waitrequest
avs_pcie_reconfig_read
avs_pcie_reconfig_readdata[15:0]
avs_pcie_reconfig_readdatavalid
avs_pcie_reconfig_clk
avs_pcie_reconfig_rstn
derr_cor_ext_rcv[1:0]
derr_rpl
derr_cor_ext_rpl
r2c_err0
r2c_err1
pme_to_cr
pme_to_sr
pm_event
pm_data
pm_auxpwr
cpl_err[6:0]
cpl_pending
refclk
pld_clk
core_clk_out
app_msi_req
app_msi_ack
app_msi_tc[2:0]
app_msi_num[4:0]
pex_msi_num[4:0]
app_int_sts
app_int_ack
Reconfiguration
Block
(optional)
Clocks
pcie_rstn
local_rstn
suc_spd_neg
ltssm[4:0]
npor
srst
crst
l2_exit
hotrst_exit
dlup_exit
reset_status
rc_pll_locked
Reset &
Link
Training
_plus
These signals are
internal for
_plus.v or .vhd)
Transceiver
Control