Altera IP Compiler for PCI Express - Manual (Page 132)

5–46 Chapter 5: IP Core Interfaces
Avalon-MM Application Interface
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Figure 5–38 shows the signals of a completer-only, single dword, IP Compiler for PCI
Express.
Figure 5–38. Signals in the Completer-Only, Single Dword, IP Core with Avalon-MM Interface
Notes to Figure 5–38 :
(1) This variant is only available in the hard IP implementation.
(2) Signals in blue are for simulation only.
tx[3:0]
rx[3:0]
pipe_mode
xphy_pll_areset
xphy_pll_locked
txdatak0_ext
txdata0_ext[7:0]
txdetectrx_ext
txelectidle0_ext
rxpolarity0_ext
txcompl0_ext
powerdown0_ext[1:0]
rxdata0_ext[7:0]
rxdatak0_ext
rxvalid0_ext
phystatus_ext
rxelectidle0_ext
rxstatus0_ext[2:0]
1-Bit Serial
RxmIrq_i
RxmReadDataValid_i
RxmWaitRequest_i
RxmAddress_o[31:0]
RxmReadData_i[31:0]
RxmByteEnable_o[3:0]
RxmWrite_o
RxmRead_o
RxmWriteData_o[31:0]
RxmResetRequest_o
32-Bit
Avalon-MM Rx
Master Port
reset_n
AvlClk_i
Clock
Reset &
Status
clk125_out
refclk
pcie_rstn
suc_spd_neg
Signals in the Completer Only Single Dword
IP Compiler for PCI Express (1)
(SOPC Builder Generated)
Hard IP
Implementation
Simulation
Only
8-Bit PIPE
Test
Interface
test_out[511:0], [63:0], or [9:0]
test_in[31:0]
(test_out is optional)
reconfig_fromgxb[:0]
reconfig_togxb[:0]
reconfig_clk
cal_blk_clk
gxb_powerdown
Transceiver
Control
(2)