Altera IP Compiler for PCI Express - Manual (Page 296)

16–8 Chapter 16: Qsys Design Example
Completing the Connections in Qsys
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
2. Connect the pcie_hard_ip_0 bar1_0 Avalon-MM master port to the
onchip_memory_0 s1 Avalon-MM slave port using the following procedure:
a. Click the bar1_0 port then hover in the Connections column to display
possible connections.
b. Click the open dot at the intersection of the onchip_memory_0 s1 port and the
pcie_hard_ip_0 bar1_0 to create a connection.
Figure 16–2 shows the Connections panel and the pcie_hard_ip_0.bar1_0 to
onchip_memory_0.s1 open Connections dot before you create the connection.
After you create the connection, the dot is filled.
3. Repeat step 2 to make the remaining connections listed in Table 16–10 .
Figure 16–2. Making the Connections in Your Qsys System: Filter Icon and First Connection
Filter Icon
Table 16–10. Complete List of Qsys Connections (Part 1 of 2)
Make Connection From: To:
pcie_hard_ip_0 pcie_core_clk Clock Output onchip_memory_0 clk1 Clock Input
pcie_hard_ip_0 pcie_core_clk Clock Output dma_0 clk Clock Input
pcie_hard_ip_0 pcie_core_reset Reset onchip_memory_0 reset1 Reset
pcie_hard_ip_0 pcie_core_reset Reset dma_0 reset Reset
pcie_hard_ip_0 bar1_0 Avalon-MM Master (step 2 ) onchip_memory_0 s1 Avalon-MM Slave (step 2 )