Ip core architecture – Altera IP Compiler for PCI Express User Manual
Page 59
August 2014
Altera Corporation
IP Compiler for PCI Express U
4. IP Core Architecture
This chapter describes the architecture of the IP Compiler for PCI Express. For the
hard IP implementation, you can design an endpoint using the Avalon-ST interface or
Avalon-MM interface, or a root port using the Avalon-ST interface. For the soft IP
implementation, you can design an endpoint using the Avalon-ST, Avalon-MM, or
Descriptor/Data interface. All configurations contain a transaction layer, a data link
layer, and a PHY layer with the following functions:
■
Transaction Layer—The transaction layer contains the configuration space, which
manages communication with the application layer: the receive and transmit
channels, the receive buffer, and flow control credits. You can choose one of the
following two options for the application layer interface from parameter editor:
■
Avalon-ST Interface
■
Descriptor/Data Interface (not recommended for new designs)
■
Data Link Layer—The data link layer, located between the physical layer and the
transaction layer, manages packet transmission and maintains data integrity at the
link level. Specifically, the data link layer performs the following tasks:
■
Manages transmission and reception of data link layer packets
■
Generates all transmission cyclical redundancy code (CRC) values and checks
all CRCs during reception
■
Manages the retry buffer and retry mechanism according to received
ACK/NAK data link layer packets
■
Initializes the flow control mechanism for data link layer packets and routes
flow control credits to and from the transaction layer
■
Physical Layer—The physical layer initializes the speed, lane numbering, and lane
width of the PCI Express link according to packets received from the link and
directives received from higher layers.
1
IP Compiler for PCI Express soft IP endpoints comply with the
. IP Compiler PCI Express hard IP endpoints and root ports
August 2014