Altera IP Compiler for PCI Express - Manual (Page 155)

Chapter 6: Register Descriptions 6–7
PCI Express Avalon-MM Bridge Control Register Content
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
The four subregions are described Table 6–11 :
1
The data returned for a read issued to any undefined address in this range is
unpredictable.
The complete map of PCI Express Avalon-MM bridge registers is shown in Table 6–12 :
Avalon-MM to PCI Express Interrupt Registers
The registers in this section contain status of various signals in the PCI Express
Avalon-MM bridge logic and allow PCI Express interrupts to be asserted when
enabled. These registers can be accessed by other PCI Express root complexes only;
however, hardware does not prevent other Avalon-MM masters from accessing them.
Table 6–13 shows the status of all conditions that can cause a PCI Express interrupt to
be asserted.
Table 6–11. Avalon-MM Control and Status Register Address Spaces
Address
Range
Address Space Usage
0x0000-0x0FFF
Registers typically intended for access by PCI Express processors only. This includes PCI Express
interrupt enable controls, write access to the PCI Express Avalon-MM bridge mailbox registers, and
read access to Avalon-MM-to-PCI Express mailbox registers.
0x1000-0x1FFF
Avalon-MM-to-PCI Express address translation tables. Depending on the system design these may be
accessed by PCI Express processors, Avalon-MM processors, or both.
0x2000-0x2FFF Reserved.
0x3000-0x3FFF
Registers typically intended for access by Avalon-MM processors only. These include Avalon-MM
Interrupt enable controls, write access to the Avalon-MM-to-PCI Express mailbox registers, and read
access to PCI Express Avalon-MM bridge mailbox registers.
Table 6–12. PCI Express Avalon-MM Bridge Register Map
Address Range Register
0x0040 PCI Express Interrupt Status Register
0x0050 PCI Express Interrupt Enable Register
0x0800-0x081F PCI Express Avalon-MM Bridge Mailbox Registers, read/write
0x0900-0x091F Avalon-MM-to-PCI Express Mailbox Registers, read-only
0x1000-0x1FFF Avalon-MM-to PCI Express Address Translation Table
0x3060 Avalon-MM Interrupt Status Register
0x3070 Avalon-MM Interrupt Enable Register
0x3A00-0x3A1F Avalon-MM-to-PCI Express Mailbox Registers, read/write
0x3B00-0x3B1F PCI Express Avalon-MM Bridge Mailbox Registers, read-only
Table 6–13. Avalon-MM to PCI Express Interrupt Status Register (Part 1 of 2) Address: 0x0040
Bit Name Access Description
[31:24] Reserved — —
[23] A2P_MAILBOX_INT7 RW1C 1 when the A2P_MAILBOX7 is written to
[22] A2P_MAILBOX_INT6 RW1C 1 when the A2P_MAILBOX6 is written to