Configuration space register access timing – Altera IP Compiler for PCI Express User Manual
Page 117
Chapter 5: IP Core Interfaces
5–31
Avalon-ST Interface
August 2014
Altera Corporation
IP Compiler for PCI Express User Guide
Configuration Space Register Access Timing
illustrates the timing of the tl_cfg_ctl interface for the Arria II GX,
Cyclone IV GX, HardCopy IV, and Stratix IV GX devices when using a 64-bit
interface.
hpg_ctrler
5
I
The hpg_ctrler signals are only available in root port mode and when the
parameter is set to On. Refer to the
and
. For endpoint variations the
hpg_ctrler
input should be hardwired to 0's. The bits have the following meanings:
[0]
Attention button pressed. This signal should be asserted when the attention
button is pressed. If no attention button exists for the slot, this bit should be
hardwired to 0, and the Attention Button Present bit (bit[0]) in the
parameter should be set to 0.
[1]
Presence detect. This signal should be asserted when a presence detect change is
detected in the slot via a presence detect circuit.
[2]
Manually-operated retention latch (MRL) sensor changed. This signal should be
asserted when an MRL sensor indicates that the MRL is Open. If an MRL Sensor
does not exist for the slot, this bit should be hardwired to 0, and the MRL Sensor
Present
bit (bit[2]) in the
[3]
Power fault detected. This signal should be asserted when the power controller
detects a power fault for this slot. If there is not a power controller for this slot
this bit should be hardwired to 0, and the Power Controller Present bit
(bit[1]) in the
[4]
Power controller status. This signal is used to set the command completed bit of
the Slot Status register. Power controller status is equal to the power controller
control signal. If there is not a power controller for this slot, this bit should be
hardwired to 0 and the Power Controller Present bit (bit[1]) in the
parameter should be set to 0.
Table 5–13. Configuration Space Signals (Hard IP Implementation) (Part 2 of 2)
Signal
Width
Dir
Description
Figure 5–28. tl_cfg_ctl Timing (Hard IP Implementation)
core_clk
pld_clk 64-bit mode
tl_cfg_ctl[31:0]
tl_cfg_add[3:0]
tl_cfg_ctl_wr
data0
data1
addr0
addr1