Altera IP Compiler for PCI Express - Manual (Page 298)

16–10 Chapter 16: Qsys Design Example
Specifying Address Assignments
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Specifying Address Assignments
Qsys requires that you resolve the base addresses of all Avalon-MM slave interfaces in
the Qsys system. You can either use the auto-assign feature, or specify the base
addresses manually. To use the auto-assign feature, on the System menu, click Assign
Base Addresses
. In the design example, you assign the base addresses manually.
The IP Compiler for PCI Express stores the base addresses in BARs. The maximum
supported size for a slave IP Compiler for PCI Express BAR is 1 GByte. Therefore,
every Avalon-MM slave base address in your system must be less than 0x20000000.
The restriction applies to all Avalon-MM slave ports that connect to an IP Compiler
for PCI Express master port.
Follow these steps to assign a base address to an Avalon-MM slave interface
manually:
1. In the row for the interface you want to export, click the Base column.
2. Type your preferred base address for the interface.
Assign the base addresses listed in Table 16–12 .
After you make these assignments, the Qsys error messages about overlapping
address ranges disappear from the Messages tab. If error messages about address
ranges remain, review the preceding steps in the chapter. If your design follows these
steps, the error messages should disappear.
reconfig_fromgxb_0 pcie_hard_ip_0_reconfig_fromgxb_0
reconfig_fromgxb_1 (1) pcie_hard_ip_0_reconfig_fromgxb_1
fixedclk pcie_hard_ip_0_fixedclk
Note to Table 16–11 :
(1) Only ×8 variations of the IP Compiler for PCI Express Qsys component have a reconfig_fromgxb_1 port. In
systems with an IP Compiler for PCI Express ×8 variation, this port connects to the upper 17 bits of the
altgxb_reconfig
block 34-bit reconfig_fromgxb port.
Table 16–11. pcie_hard_ip_0 Exported Interfaces (Part 2 of 2)
Interface Name Exported Name
Table 16–12. Base Address Assignments for Avalon-MM Slave Interfaces
Interface Name Exported Name
pcie_hard_ip_0 txs 0x00000000
pcie_hard_ip_0 cra 0x00000000
dma_0 control_port_slave 0x00004000
onchip_memory_0 s1 0x00200000