Altera IP Compiler for PCI Express - Manual (Page 153)

Chapter 6: Register Descriptions 6–5
Configuration Space Register Content
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Table 6–8 describes the PCI Express capability structure for specification version 2.0.
Table 6–9 describes the virtual channel capability structure.
Table 6–8. PCI Express Capability Structure Version 2.0, Rev2 Spec: PCI Express Capabilities Register and PCI Express
Capability List Register
Byte Offset 31:16 15:8 7:0
0x080 PCI Express Capabilities Register Next Cap Pointer PCI Express Cap ID
0x084 Device Capabilities
0x088 Device Status Device Control 2
0x08C Link Capabilities
0x090 Link Status Link Control
0x094 Slot Capabilities
0x098 Slot Status Slot Control
0x09C Root Capabilities Root Control
0x0A0 Root Status
0x0A4 Device Capabilities 2
0x0A8 Device Status 2
Device Control 2
Implement completion timeout disable
0x0AC Link Capabilities 2
0x0B0 Link Status 2 Link Control 2
0x0B4 Slot Capabilities 2
0x0B8 Slot Status 2 Slot Control 2
Note to Table 6–8 :
(1) Registers not applicable to a device are reserved.
(2) Refer to Table 6–23 on page 6–12 for a comprehensive list of correspondences between the configuration space registers and the PCI Express
Base Specification 2.0.
Table 6–9. Virtual Channel Capability Structure, Rev2 Spec: Virtual Channel Capability (Part 1 of 2)
Byte Offset 31:24 23:16 15:8 7:0
0x100 Next Cap PTR Vers. Extended Cap ID
0x104 ReservedP
Port VC Cap 1
Number of low-priority VCs
0x108 VAT offset ReservedP VC arbit. cap
0x10C Port VC Status Port VC control
0x110 PAT offset 0 (31:24) VC Resource Capability Register (0)
0x114 VC Resource Control Register (0)
0x118 VC Resource Status Register (0) ReservedP
0x11C PAT offset 1 (31:24) VC Resource Capability Register (1)
0x120 VC Resource Control Register (1)
0x124 VC Resource Status Register (1) ReservedP
...
0x164 PAT offset 7 (31:24) VC Resource Capability Register (7)