Altera IP Compiler for PCI Express User Manual
Page 367
Chapter :
Info–7
Revision History
August 2014
Altera Corporation
IP Compiler for PCI Express User Guide
November
2008
8.1
■
Added new material on root port which is available for the hard IP implementation in
Stratix IV GX devices.
■
Changed to full support for Gen2 ×8 in the Stratix IV GX device.
■
Added discussion of dynamic reconfiguration of the transceiver for Stratix IV GX devices.
Refer to Table 5–29.
■
Updated Resource Usage and Performance numbers for Quartus II 8.1 software
■
Added text explaining where TX I/Os are constrained. (Chapter 1)
■
Corrected Number of Address Pages in Table 3–6.
■
Revised the Table 9–2 on page 9–2. The following message types Assert_INTB,
Assert_INTC, Assert_INTD, Deassert_INTB, Deassert_INTC and Deassert_INTD are not
generated by the core.
■
Clarified definition of rx_ack. It cannot be used to backpressure rx_data.
■
Corrected descriptions of cpl_err[4] and cpl_err[5] which were reversed. Added the
fact that the cpl_err signals are pulsed for 1 cycle.
■
Corrected 128-bit RX data layout in Figure 5–9, Figure 5–10, Figure 5–11, Figure 5–12,
Figure 5–18, Figure 5–19, and Figure 5–20.
■
Added explanation that for tx_cred port, completion header, posted header, non-
posted header
and non-posted data fields, a value of 7 indicates 7 or more available
credits.
■
Added warning that in the Cyclone III designs using the external PHY must not use the dual-
purpose V
REF
pins.
■
Revised
. For 8.1 txclk goes through a flip flop and is not inverted.
■
Corrected (reversed) positions of the SMI and EPLAST_ENA bits in
.
■
Added note that the RC slave module which is by default not instantiated in the
must be instantiated to avoid deadline in designs that
interface to a commercial BIOS.
■
Added definitions for test_out in hard IP implementation.
■
Removed description of Training error bit which is not supported in PCI Express
Specifications 1.1, 2.0 or 1.0a for endpoints.
266573
278539
Date
Version
Changes Made
SPR