Stratix iii family, Stratix iv family, Avalon-mm interface – Altera IP Compiler for PCI Express User Manual
Page 357
Chapter :
C–3
Avalon-MM Interface
August 2014
Altera Corporation
IP Compiler for PCI Express User Guide
Stratix III Family
shows the typical expected performance and resource utilization of
Stratix III (EP3SL200F1152C2) devices for a maximum payload of 256 bytes with
different parameters, using the Quartus II software, version 11.0.
Stratix IV Family
shows the typical expected performance and resource utilization of
Stratix IV GX (EP3SGX290FH29C2X) devices for a maximum payload of 256 bytes
with different parameters, using the Quartus II software, version 11.0.
Avalon-MM Interface
This section tabulates the typical expected performance and resource utilization for
the soft IP implementation for various parameters when using the Stratix IV Family
Table C–4. Performance and Resource Utilization, Avalon-ST Interface - Stratix III Family
Parameters
Size
×1/ ×4
Internal
Clock (MHz)
Virtual
Channels
Combinational
ALUTs
Logic
Registers
M9K Memory
Blocks
M144K Memory
Blocks
×1
125
1
5300
4500
5
0
×1
125
2
6800
5900
9
0
×1
62.5
1
5500
4800
5
0
×1
62.5
2
6800
6000
11
1
×4
125
1
7000
5300
8
0
×4
125
2
8500
6500
15
0
Note to
(1) C4 device used.
(2) C3 device used.
Table C–5. Performance and Resource Utilization, Avalon-ST Interface - Stratix IV Family
Parameters
Size
×1/ ×4
Internal
Clock (MHz)
Virtual
Channels
Combinational
ALUTs
Logic
Registers
M9K Memory
Blocks
M144K
×1
125
1
5500
4100
9
0
×1
125
2
6900
5200
14
0
×4
125
1
7100
5100
10
1
×4
125
2
8500
6200
18
0