Altera IP Compiler for PCI Express - Manual (Page 294)

16–6 Chapter 16: Qsys Design Example
Adding the Remaining Components to the Qsys System
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
1 The values displayed for Posted header credit, Posted data credit,
Non-posted header credit
, Completion header credit, and Completion
data credit are read-only. The values are computed based on the values set
for Maximum payload size and RX buffer credit allocation – performance
for received requests
.
7. Under the Avalon-MM Settings heading, specify the settings in Table 16–6 .
8. Under the Address Translation heading, specify the settings in Table 16–7 .
You can ignore the Address Translation Table Contents, as they are valid only for
the Fixed translation table configuration.
9. Click Finish to add the IP Compiler for PCI Express component pcie_hard_ip_0 to
your Qsys system.
1
Your system is not yet complete, so you can ignore any error messages generated by
Qsys at this stage.
Adding the Remaining Components to the Qsys System
This section describes adding the DMA controller and on-chip memory to your Qsys
system.
1. To add the DMA Controller component to your system, from the System Contents
tab, under Bridges and Adapters in the DMA folder, double-click the DMA
Controller
component. This component contains read and write master ports and
a control port slave.
2. In the DMA Controller parameter editor, specify the settings in Table 16–8 .
Table 16–6. Avalon-MM Settings
Parameter Value
Peripheral Mode Requester/Completer
Control Register Access (CRA) Avalon slave port Turn this option on
Auto Enable PCIe Interrupt (enabled at power-on) Turn this option off
Table 16–7. Address Translation Settings
Parameter Value
Address Translation Table Configuration Dynamic translation table
Number of address pages 2
Size of address pages 1 MByte - 20 bits
Table 16–8. DMA Controller Parameters
Parameter Value
Width of the DMA length register 13
Enable burst transfers Turn this option on
Maximum burst size 128