Altera IP Compiler for PCI Express - Manual (Page 143)

Chapter 5: IP Core Interfaces 5–57
Physical Layer Interface Signals
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
for simulation of the PIPE interface for variations using an internal transceiver. In
Table 5–31 , signals that include lane number 0 also exist for lanes 1-7, as marked in the
table. Refer to Chapter 14, External PHYs for descriptions of the slightly modified
PIPE interface signalling for use with specific external PHYs. The modifications
include DDR signalling and source synchronous clocking in the TX direction.
Table 5–31. PIPE Interface Signals (Part 1 of 2)
Signal Name in
Qsys
I/O Description
txdata_ext[15:0]/
pipe_ext_txdata0_ext[15:0] (1)
O
Transmit data (2 symbols on lane ). This bus transmits data on
lane . The first transmitted symbol is txdata_ext[7:0] and the
second transmitted symbol is txdata0_ext[15:8]. For the 8-bit PIPE
mode only txdata_ext[7:0] is available.
txdatak_ext[1:0]/
pipe_ext_txdatak_ext[1:0] (1)
O
Transmit data control (2 symbols on lane ). This signal serves
as the control bit for txdata_ext; txdatak_ext[0] for the
first transmitted symbol and txdatak_ext[1] for the second
(8B/10B encoding). For 8-bit PIPE mode only the single bit signal
txdatak
_ext is available.
txdetectrx_ext/
pipe_ext_txdetectrx_ext (1)
O
Transmit detect receive . This signal tells the PHY layer to start a
receive detection operation or to begin loopback.
txelecidle_ext/
pipe_ext_txelecidle_ext (1)
O
Transmit electrical idle . This signal forces the transmit output to
electrical idle.
txcompl_ext/
pipe_ext_txcompl_ext (1)
O
Transmit compliance . This signal forces the running disparity to
negative in compliance mode (negative COM character).
rxpolarity_ext/
pipe_ext_rxpolarity_ex (1)
O
Receive polarity . This signal instructs the PHY layer to do a polarity
inversion on the 8B/10B receiver decoding block.
powerdown_ext[1:0]/
pipe_ext_powerdown_ext[1:0] (1)
O
Power down . This signal requests the PHY to change its power state
to the specified state (P0, P0s, P1, or P2).
tx_pipemargin/ internal signal in Qsys O
Transmit V
OD
margin selection. The IP Compiler for PCI Express hard IP
sets the value for this signal based on the value from the Link Control 2
Register. Available for simulation only.
tx_pipedeemph/internal signal in
Qsys
O
Transmit de-emphasis selection. In PCI Express Gen2 (5 Gbps) mode it
selects the transmitter de-emphasis:
■ 1'b0: -6 dB
■ 1'b1: -3.5 dB
The PCI Express IP core hard IP sets the value for this signal based on
the indication received from the other end of the link during the Training
Sequences (TS). You do not need to change this value.
rxdata_ext[15:0]/
pipe_ext_rxdata_ext[15:0]
(1) (2)
I
Receive data (2 symbols on lane ). This bus receives data on
lane . The first received symbol is rxdata_ext[7:0] and the
second is rxdata_ext[15:8]. For the 8 Bit PIPE mode only
rxdata_ext[7:0]
is available.
rxdatak_ext[1:0]/
pipe_ext_rxdatak_ext[1:0]
(1) (2)
I
Receive data control (2 symbols on lane ). This signal separates
control and data symbols. The first symbol received is aligned with
rxdatak_ext[0]
and the second symbol received is aligned with
rxdata_ext[1] . For the 8 Bit PIPE mode only the single bit signal
rxdatak_ext is available.
rxvalid_ext (1) (2) I
Receive valid . This symbol indicates symbol lock and valid data on
rxdata_ext
and rxdatak_ext.