Altera IP Compiler for PCI Express - Manual (Page 60)

4–2 Chapter 4: IP Core Architecture
Application Interfaces
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Figure 4–1 broadly describes the roles of each layer of the PCI Express IP core.
This chapter provides an overview of the architecture of the Altera IP Compiler for
PCI Express. It includes the following sections:
■ Application Interfaces
■ Transaction Layer
■ Data Link Layer
■ Physical Layer
■ PCI Express Avalon-MM Bridge
■ Completer Only PCI Express Endpoint Single DWord
Application Interfaces
You can generate the IP Compiler for PCI Express with the following application
interfaces:
■ Avalon-ST Application Interface
■ Avalon-MM Interface
Appendix B describes the Descriptor/Data interface.
Avalon-ST Application Interface
You can create an IP Compiler for PCI Express root port or endpoint using the
parameter editor to specify the Avalon-ST interface. It includes a PCI Express
Avalon-ST adapter module in addition to the three PCI Express layers.
Figure 4–1. IP Compiler for PCI Express Layers
Tx
Rx
Transaction Layer Data Link Layer Physical Layer
IP Compiler for PCI Express
To Application Layer To Link
Application Interfaces
Avalon-ST Interface
Data/Descriptor
Interface
Avalon-MM Interface
Tx Port
Rx Port
or
or
With information sent
by the application
layer, the transaction
layer generates a TLP,
which includes a
header and, optionally,
a data payload. The physical layer
encodes the packet
and transmits it to the
receiving device on the
other side of the link.
The transaction layer
disassembles the
transaction and
transfers data to the
application layer in a
form that it recognizes. The data link layer
verifies the packet's
sequence number and
checks for errors. The physical layer
decodes the packet
and transfers it to the
data link layer.
The data link layer
ensures packet
integrity, and adds a
sequence number and
link cyclic redundancy
code (LCRC) check to
the packet.