Altera IP Compiler for PCI Express - Manual (Page 159)

Chapter 6: Register Descriptions 6–11
PCI Express Avalon-MM Bridge Control Register Content
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
The interrupt status register ( Table 6–19 ) records the status of all conditions that can
cause an Avalon-MM interrupt to be asserted.
An Avalon-MM interrupt can be asserted for any of the conditions noted in the
Avalon-MM interrupt status register by setting the corresponding bits in the interrupt
enable register (
Table 6–20 ).
PCI Express interrupts can also be enabled for all of the error conditions described.
However, it is likely that only one of the Avalon-MM or PCI Express interrupts can be
enabled for any given bit. There is typically a single process in either the PCI Express
or Avalon-MM domain that is responsible for handling the condition reported by the
interrupt.
Avalon-MM Mailbox Registers
A processor local to the system interconnect fabric typically requires write access to a
set of Avalon-MM-to-PCI Express mailbox registers and read-only access to a set of
PCI Express-to-Avalon-MM mailbox registers. Eight mailbox registers are available.
The Avalon-MM-to-PCI Express mailbox registers are writable at the addresses shown
in
Table 6–21 . When the Avalon-MM processor writes to one of these registers the
corresponding bit in the PCI Express interrupt status register is set to 1.
Table 6–19. PCI Express to Avalon-MM Interrupt Status Register Address: 0x3060
Bits Name Access Description
[15:0] Reserved — —
[16] P2A_MAILBOX_INT0 RW1C 1 when the P2A_MAILBOX0 is written
[17] P2A_MAILBOX_INT1 RW1C 1 when the P2A_MAILBOX1 is written
[18] P2A_MAILBOX_INT2 RW1C 1 when the P2A_MAILBOX2 is written
[19] P2A_MAILBOX_INT3 RW1C 1 when the P2A_MAILBOX3 is written
[20] P2A_MAILBOX_INT4 RW1C 1 when the P2A_MAILBOX4 is written
[21] P2A_MAILBOX_INT5 RW1C 1 when the P2A_MAILBOX5 is written
[22] P2A_MAILBOX_INT6 RW1C 1 when the P2A_MAILBOX6 is written
[23] P2A_MAILBOX_INT7 RW1C 1 when the P2A_MAILBOX7 is written
[31:24] Reserved — —
Table 6–20. PCI Express to Avalon-MM Interrupt Enable Register Address: 0x3070
Bits Name Access Description
[15:0] Reserved — —
[23:16] P2A_MB_IRQ RW
Enables assertion of Avalon-MM interrupt CraIrq_o signal when
the specified mailbox is written by the root complex.
[31:24] Reserved — —
Table 6–21. Avalon-MM-to-PCI Express Mailbox Registers, Read/Write (Part 1 of 2) Address Range: 0x3A00-0x3A1F
Address Name Access Description
0x3A00 A2P_MAILBOX0 RW Avalon-MM-to-PCI Express mailbox 0
0x3A04 A2P _MAILBOX1 RW Avalon-MM-to-PCI Express mailbox 1