Altera IP Compiler for PCI Express - Manual (Page 311)

Chapter 17: Debugging 17–3
Link and Transceiver Testing
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
If you are using the soft IP implementation of the IP Compiler for PCI Express, you
can see the PIPE interface at the pins of your device. If you are using the hard IP
implementation, you can monitor the PIPE signals through the test_out bus.
f The PHY Interface for PCI Express Architecture specification is available on the Intel
website (
www.intel.com ).
Use Third-Party PCIe Analyzer
A third-party PCI Express logic analyzer records the traffic on the physical link and
decodes traffic, saving you the trouble of translating the symbols yourself. A
third-party PCI Express logic analyzer can show the two-way traffic at different levels
for different requirements. For high-level diagnostics, the analyzer shows the LTSSM
flows for devices on both side of the link side-by-side. This display can help you see
the link training handshake behavior and identify where the traffic gets stuck. A PCIe
traffic analyzer can display the contents of packets so that you can verify the contents.
For complete details, refer to the third-party documentation.
BIOS Enumeration Issues
Both FPGA programming (configuration) and the PCIe link initialization require time.
There is some possibility that Altera FPGA including an IP Compiler for PCI Express
may not be ready when the OS/BIOS begins enumeration of the device tree. If the
FPGA is not fully programmed when the OS/BIOS begins its enumeration, the OS
does not include the IP Compiler for PCI Express module in its device map. To
eliminate this issue, you can do a soft reset of the system to retain the FPGA
programming while forcing the OS/BIOS to repeat its enumeration.
Configuration Space Settings
Check the actual configuration space settings in hardware to verify that they are
correct. You can do so using one of the following two tools:
■ PCItree (in Windows)–PCItree is a third-party tool that allows you to see the actual
hardware configuration space in the PCIe device. It is available on the PCI Tree
website (
www.pcitree.de/index.html ).
■ lspci (in Linux)–lspci is a Linux command that allows you to see actual hardware
configuration space in the PCI devices. Both first, 64 bytes and extended
configuration space of the device are listed. Refer to the lspci Linux man page
(
linux.die.net/man/8/lspci ) for more usage options. You can find this command in
your /sbin directory.
Link and Transceiver Testing
In Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX devices, the IP
Compiler for PCI Express hard IP implementation supports a reverse parallel
loopback path you can use to test the IP Compiler for PCI Express endpoint link
implementation from a working PCI Express root complex. For more information
about this loopback path, refer to
“Reverse Parallel Loopback” on page 4–17 .
This section tells you how to configure and use the reverse parallel loopback path in
your IP Compiler for PCI Express system.