Altera IP Compiler for PCI Express - Manual (Page 85)

Chapter 4: IP Core Architecture 4–27
Completer Only PCI Express Endpoint Single DWord
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
The RX block passes header information to the Avalon-MM master, which generates
the corresponding transaction to the Avalon-MM interface. The bridge accepts no
additional requests while a request is being processed. While processing a read
request, the RX block deasserts the ready signal until the TX block sends the
corresponding completion packet to the hard IP block. While processing a write
request, the RX block sends the request to the Avalon-MM system interconnect fabric
before accepting the next request.
Avalon-MM RX Master Block
The 32-bit Avalon-MM master connects to the Avalon-MM system interconnect fabric.
It drives read and write requests to the connected Avalon-MM slaves, performing the
required address translation. The RX master supports all legal combinations of byte
enables for both read and write requests.
f For more information about legal combinations of byte enables, refer to Chapter 3,
Avalon Memory-Mapped Interfaces in the
Avalon Interface Specifications.
IP Compiler for PCI Express TX Block
The TX block sends completion information to the IP Compiler for PCI Express hard
IP block. The IP core then sends this information to the root complex. The TX
completion block generates a completion packet with Completer Abort (CA) status
and no completion data for unsupported requests. The TX completion block also
supports the zero-length read (flush) command.
Interrupt Handler Block
The interrupt handler implements both INTX and MSI interrupts. The msi_enable bit
in the configuration register specifies the interrupt type. The msi_enable_bit is part
of MSI message control portion in MSI Capability structure. It is bit[16] of 0x050 in the
configuration space registers. If the msi_enable bit is on, an MSI request is sent to the
IP Compiler for PCI Express when received, otherwise INTX is signaled. The interrupt
handler block supports a single interrupt source, so that software may assume the
source. You can disable interrupts by leaving the interrupt signal unconnected in the
interrupt signals unconnected in the IRQ column of Qsys. When the MSI registers in
the configuration space of the completer only single dword IP Compiler for PCI
Express are updated, there is a delay before this information is propagated to the
Bridge module. You must allow time for the Bridge module to update the MSI register
information. Under normal operation, initialization of the MSI registers should occur
substantially before any interrupt is generated. However, failure to wait until the
update completes may result in any of the following behaviors:
■ Sending a legacy interrupt instead of an MSI interrupt
■ Sending an MSI interrupt instead of a legacy interrupt
■ Loss of an interrupt request