Altera IP Compiler for PCI Express - Manual (Page 348)

B–30 Chapter :
Incremental Compile Module for Descriptor/Data Examples
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
RX Datapath
The RX datapath contains the RX boundary registers (for incremental compile) and a
bridge to transport data from the IP Compiler for PCI Express interface to the
Avalon-ST interface. The bridge autonomously acks all packets received from the IP
Compiler for PCI Express. For simplicity, the rx_abort and rx_retry features of the IP
core are not used, and RX_mask is loosely supported. (Refer to
Table B–14 on page B–32
for further details.) The RX datapath also provides an optional message-dropping
feature that is enabled by default. The feature acknowledges PCI Express message
packets from the IP Compiler for PCI Express, but does not pass them to the user
application. The user can optionally allow messages to pass to the application by
setting the DROP_MESSAGE parameter in altpcierd_icm_rxbridge.v to 1’b0. The
latency through the ICM RX datapath is approximately four clock cycles.
TX Datapath
The TX datapath contains the TX boundary registers (for incremental compile) and a
bridge to transport data from the Avalon-ST interface to the IP Compiler for PCI
Express interface. A data FIFO buffers the Avalon-ST data from the user application
until the IP Compiler for PCI Express accepts it. The TX datapath also implements an
NPBypass function for deadlock prevention. When the IP Compiler for PCI Express
runs out of non-posted (NP) credits, the ICM allows completions and posted requests
to bypass NP requests until credits become available. The ICM handles any NP
requests pending in the ICM when credits run out and asserts the tx_mask signal to
the user application to indicate that it should stop sending NP requests. The latency
through the ICM TX datapath is approximately five clock cycles.
MSI Datapath
The MSI datapath contains the MSI boundary registers (for incremental compile) and
a bridge to transport data from the Avalon-ST interface to the IP Compiler for PCI
Express interface. The ICM maintains packet ordering between the TX and MSI
datapaths. In this design example, the MSI interface supports low-bandwidth MSI
requests. For example, not more than one MSI request can coincide with a single TX
packet. The MSI interface assumes that the MSI function in the IP Compiler for PCI
Express is enabled. For other applications, you may need to modify this module to
include internal buffering, MSI-throttling at the application, and so on.
Sideband Datapath
The sideband interface contains boundary registers for non-timing critical signals
such as configuration signals. (Refer to
Table B–17 on page B–36 for details.)
ICM Files
This section lists and briefly describes the ICM files. The IP Compiler for PCI Express
parameter editor generates all these ICM files and places them in the
< variation name>_examples\common\incremental_compile_module folder.