Altera IP Compiler for PCI Express - Manual (Page 100)

5–14 Chapter 5: IP Core Interfaces
Avalon-ST Interface
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Figure 5–14 illustrates the timing of the RX interface when the application
backpressures the IP Compiler for PCI Express by deasserting rx_st_ready. The
rx_st_valid
signal must deassert within three cycles after rx_st_ready is deasserted.
In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is held until
the application is able to accept it.
Figure 5–15 illustrates the timing of the Avalon-ST RX interface. On this interface, the
core deasserts rx_st_valid in response to the deassertion of rx_st_ready from the
application.
Figure 5–14. 128-Bit Application Layer Backpressures Hard IP Transaction Layer
clk
rx_st_data[127:0]
rx_st_sop
rx_st_eop
rx_st_empty
rx_st_ready
rx_st_valid
rx_st_err
0000 .
Figure 5–15. Avalon-ST RX Interface Timing
clk
rx_st_ready
rx_st_valid
rx_st_data[63:0]
rx_st_sop
rx_st_eop
h1 h2 data0 data1 data2 data3 data4 data5 data6
3 cycles
max latency
1 2 3 4 5 6 7 8 9 11 10