Altera IP Compiler for PCI Express - Manual (Page 356)

C–2 Chapter :
Avalon-ST Interface
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Arria II GX Devices
Table C–2 shows the typical expected performance and resource utilization of
Arria II GX (EP2AGX125EF35C4) devices for different parameters with a maximum
payload of 256 bytes using the Quartus II software, version 11.0.
Stratix II GX Devices
Table C–3 shows the typical expected performance and resource utilization of
Stratix II and Stratix II GX (EP2SGX130GF1508C3) devices for a maximum payload of
256 bytes for devices with different parameters, using the Quartus II software, version
11.0.
Table C–2. Performance and Resource Utilization, Avalon-ST Interface–Arria GX Devices
(Note 1)
Parameters Size
×1/ ×4
Internal
Clock (MHz)
Virtual
Channel
Combinational
ALUTs
Logic
Registers
M9K
×1 125 1 5300 4000 9
×1 125 2 6800 5200 14
×4 125 1 6900 5000 11
×4 125 2 8400 6200 18
Note to Table C–1 :
(1) This configuration only supports Gen1.
Table C–3. Performance and Resource Utilization, Avalon-ST Interface - Stratix II and
Stratix II GX Devices
Parameters Size
×1/ ×4
×8
Internal
Clock (MHz)
Virtual
Channels
Combinational
ALUTs
Logic
Registers
Memory Blocks
M512 M4K
×1 125 1 5400 4000 2 13
×1 125 2 7000 5200 3 19
×4 125 1 6900 4900 6 17
×4 125 2 8500 6100 7 27
×8 250 1 6300 5900 10 15
×8 250 2 7600 7000 10 23