Altera IP Compiler for PCI Express - Manual (Page 193)

Chapter 10: Interrupts 10–3
MSI-X
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Figure 10–4 illustrates the interactions among MSI interrupt signals for the root port
in Figure 10–3 . The minimum latency possible between app_msi_req and app_msi_ack
is one clock cycle.
MSI-X
You can enable MSI-X interrupts by turning on Implement MSI-X on the Capabilities
page using the parameter editor. If you turn on the Implement MSI-X option, you
should implement the MSI-X table structures at the memory space pointed to by the
BARs as part of your application.
MSI-X TLPs are generated by the application and sent through the transmit interface.
They are single dword memory writes so that Last DW Byte Enable in the TLP header
must be set to 4b’0000. MSI-X TLPs should be sent only when enabled by the MSI-X
enable and the function mask bits in the message control for MSI-X configuration
register. In the hard IP implementation, these bits are available on the tl_cfg_ctl
output bus.
f
For more information about implementing the MSI-X capability structure, refer
Section 6.8.2. of the
PCI Local Bus Specification, Revision 3.0 .
Legacy Interrupts
Legacy interrupts are signaled on the PCI Express link using message TLPs that are
generated internally by the IP Compiler for PCI Express. The app_int_sts input port
controls interrupt generation. When the input port asserts app_int_sts, it causes an
Assert_INTA
message TLP to be generated and sent upstream. Deassertion of the
app_int_sts input port causes a Deassert_INTA message TLP to be generated and
sent upstream. Refer to Figure 10–5 and Figure 10–6 .
Figure 10–4. MSI Interrupt Signals Waveform
Note to Figure 10–4 :
(1) For variants using the Avalon-ST interface, app_msi_req can extend beyond app_msi_ack before deasserting. For
descriptor/data variants, app_msi_req must deassert on the cycle following app_msi_ack
clk
app_msi_req
app_msi_tc[2:0]
app_msi_num[4:0]
app_msi_ack
1 2 3 5 6 4
valid
valid