Chained_dma_test procedure, Dma_rd_test procedure – Altera IP Compiler for PCI Express User Manual

Page 283

Chapter 15: Testbench and Design Example

15–51

BFM Procedures and Functions

August 2014

Altera Corporation

IP Compiler for PCI Express User Guide

Procedures and Functions Specific to the Chaining DMA Design Example

This section describes procedures that are specific to the chaining DMA design
example. These procedures are located in the VHDL entity file
altpcietb_bfm_driver_chaining.vhd

or the Verilog HDL module file

altpcietb_bfm_driver_chaining.v

chained_dma_test Procedure

The chained_dma_test procedure is the top-level procedure that runs the chaining
DMA read and the chaining DMA write

dma_rd_test Procedure

Use the dma_rd_test procedure for DMA reads from the endpoint memory to the
BFM shared memory.

Argument range

vec

Input data type reg with a range of 31:0.

Return range

string

Returns a 7-digit decimal representation of the input argument that is padded with
leading 0s if necessary. Return data is type reg with a range of 56:1.

Returns the letter <U> if the value cannot be represented.

Table 15–59. dimage7

Table 15–60. chained_dma_test Procedure

Location

altpcietb_bfm_driver_chaining.v or altpcietb_bfm_driver_chaining.vhd

Syntax

chained_dma_test (bar_table, bar_num, direction, use_msi, use_eplast)

Arguments

bar_table

Address of the endpoint bar_table structure in BFM shared memory.

bar_num

BAR number to analyze.

direction

When 0 the direction is read.

When 1 the direction is write.

Use_msi

When set, the root port uses native PCI Express MSI to detect the DMA completion.

Use_eplast

When set, the root port uses BFM shared memory polling to detect the DMA completion.

Table 15–61.

dma_rd_test

Procedure