Altera IP Compiler for PCI Express User Manual
Page 62

4–4
Chapter 4: IP Core Architecture
Application Interfaces
IP Compiler for PCI Express User Guide
August 2014
Altera Corporation
illustrate the hard IP and soft IP implementations of the IP
Compiler for PCI Express with an Avalon-ST interface.
Figure 4–3. PCI Express Hard IP Implementation with Avalon-ST Interface to User Application
Figure 4–4. PCI Express Soft IP Implementation with Avalon-ST Interface to User Application
Clock
Domain
Crossing
(CDC)
Data
Link
Layer
(DLL)
Transaction Layer
(TL)
PHYMAC
IP Compiler for PCI Express Hard IP Implementation
Avalon-ST Rx
Avalon-ST Tx
Side Band
LMI
(Avalon-MM)
PCIe Reconfig
PIPE
Adapter
T
o
Application La
y
e
r
LMI
Reconfig
Block
Clock & Reset
Selection
Transceiver
Configuration
Space
Data
Link
Layer
(DLL)
Transaction Layer
(TL)
PHYMAC
Avalon-ST Rx
Avalon-ST Tx
Side Band
Test_in/Test_out
PIPE
Adapter
T
o
Application La
y
e
r
Test
Clock & Reset
Selection
Transceiver
IP Compiler for PCI Express Soft IP Implementation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)