Altera IP Compiler for PCI Express - Manual (Page 152)

6–4 Chapter 6: Register Descriptions
Configuration Space Register Content
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Table 6–5 describes the MSI-X capability structure.
Table 6–6 describes the power management capability structure.
Table 6–7 describes the PCI Express capability structure for specification versions 1.0a
and 1.1.
Table 6–5. MSI-X Capability Structure, Rev2 Spec: MSI and MSI-X Capability Structures
Byte Offset 31:24 23:16 15:8 7:3 2:0
0x068
Message Control
MSI-X Table size [26:16]
Next Cap Ptr Capability ID
0x06C MSI-X Table Offset
BAR
Indicator
(BIR)
Note to Table 6–5 :
(1) Refer to Table 6–23 on page 6–12 for a comprehensive list of correspondences between the configuration space registers and the PCI Express
Base Specification 2.0.
Table 6–6. Power Management Capability Structure, Rev2 Spec: Power Management Capability Structure
Byte Offset 31:24 23:16 15:8 7:0
0x078 Capabilities Register Next Cap PTR Cap ID
0x07C Data
PM Control/Status
Bridge Extensions
Power Management Status & Control
Note to Table 6–6 :
(1) Refer to Table 6–23 on page 6–12 for a comprehensive list of correspondences between the configuration space registers and the PCI Express
Base Specification 2.0.
Table 6–7. PCI Express Capability Structure Version 1.0a and 1.1 (Note 1) , Rev2 Spec: PCI Express Capabilities
Register and PCI Express Capability List Register
Byte Offset 31:24 23:16 15:8 7:0
0x080 PCI Express Capabilities Register Next Cap Pointer PCI Express Cap ID
0x084 Device Capabilities
0x088 Device Status Device Control
0x08C Link Capabilities
0x090 Link Status Link Control
0x094 Slot Capabilities
0x098 Slot Status Slot Control
0x09C Reserved Root Control
0x0A0 Root Status
Note to Table 6–7 :
(1) Reserved and preserved. As per the PCI Express Base Specification 1.1, this register is reserved for future RW implementations. Registers are
read-only and must return 0 when read. Software must preserve the value read for writes to bits.
(2) Refer to Table 6–23 on page 6–12 for a comprehensive list of correspondences between the configuration space registers and the PCI Express
Base Specification 2.0.