Altera IP Compiler for PCI Express - Manual (Page 300)

16–12 Chapter 16: Qsys Design Example
Generating the Qsys System
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Figure 16–4 illustrates the complete Qsys system.
Generating the Qsys System
To generate the Qsys system, follow these steps:
1. On the Generation tab, in the Simulation section, set the following options:
■ For Create simulation model, select Verilog.
■ For Create testbench Qsys system, select Standard, BFMs for standard
Avalon interfaces
.
■ For Create testbench simulation model, select Verilog.
2. In the Synthesis section, turn on Create HDL design files for synthesis.
3. Click the Generate button at the bottom of the tab.
4. After Qsys reports Generate Completed in the Generate progress box title, click
Close .
5. On the File menu, click Save.
Figure 16–4. Complete IP Compiler for PCI Express Example Design Qsys System