Altera IP Compiler for PCI Express - Manual (Page 366)

Info–6 Chapter :
Revision History
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
February 2009 9.0
■ Updated Table 1–8 on page 1–11 and Table 1–9 on page 1–13. Removed tx_swing signal.
■ Added device support for Arria II GX in both the hard and soft IP implementations. Added
preliminary support for HardCopy III and HardCopy IV E.
■ Added support for hard IP endpoints in the SOPC Builder design flow.
■ Added PCI Express reconfiguration block for dynamic reconfiguration of configuration space
registers. Updated figures to show this block.
■ Enhanced Chapter 15, Testbench and Design Example to include default instantiation of the
RC slave module, tests for ECRC and PCI Express dynamic reconfiguration.
■ Changed Chapter 16, SOPC Builder Design Example to demonstrate use of interrupts.
■ Improved documentation of MSI.
■ Added definitions of DMA read and writes status registers in Chapter 15, Testbench and
Design Example.
■ Added the following signals to the hard IP implementation of root port and endpoint using
the MegaWizard Plug-In Manager design flow: tx_pipemargin, tx_pipedeemph,
tx_swing
(PIPE interface), ltssm[4:0], and lane_act[3:0] (Test interface).
■ Added recommendation in “Avalon Configuration Settings” on page 3–15 that when the
Avalon Configuration selects a dynamic translation table that multiple address translation
table entries be employed to avoid updating a table entry before outstanding requests
complete.
■ Clarified that ECC support is only available in the hard IP implementation.
■ Updated Figure 4–7 on page 4–9 to show connections between the Type 0 Configuration
Space register and all virtual channels.
■ Made the following corrections to description of Chapter 3, Parameter Settings:
■ The enable rate match FIFO is available for Stratix IV GX
■ Completion timeout is available for v2.0
■ MSI-X Table BAR Indicator (BIR) value can range 1:0–5:0 depending on BAR settings
■ Changes in “Power Management Parameters” on page 3–13: L0s acceptable latency is
<= 4
μs, not < 4 μs; L1 acceptable latency is <= 64 μs, not < 64 μs, L1 exit latency
common clock is <= 64 μs, not < 64 μs, L1 exit latency separate clock is <= 64 μs, not <
64 μs
■ N_FTS controls are disabled for Stratix IV GX pending devices characterization
Date Version Changes Made SPR