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Receive buffer reordering – Altera IP Compiler for PCI Express User Manual

Page 180

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8–4

Chapter 8: Transaction Layer Protocol (TLP) Details

Receive Buffer Reordering

IP Compiler for PCI Express User Guide

August 2014

Altera Corporation

The transaction layer sends all memory and I/O requests, as well as completions
generated by the application layer and passed to the transmit interface, to the PCI
Express link.

The IP core can generate and transmit power management, interrupt, and error
signaling messages automatically under the control of dedicated signals.
Additionally, the IP core can generate MSI requests under the control of the
dedicated signals.

Receive Buffer Reordering

The receive datapath implements a receive buffer reordering function that allows
posted and completion transactions to pass non-posted transactions (as allowed by
PCI Express ordering rules) when the application layer is unable to accept additional
non-posted transactions.

The application layer dynamically enables the RX buffer reordering by asserting the
rx_mask

signal. The rx_mask signal masks non-posted request transactions made to

the application interface so that only posted and completion transactions are
presented to the application.

Table 8–2

lists the transaction ordering rules.

Table 8–2. Transaction Ordering Rules (Part 1 of 2)

(Note 1)

(12)

Row Pass Column

Posted Request

Non Posted Request

Completion

Memory Write or

Message

Request

Read Request

I/O or Cfg Write

Request

Read Completion

I/O or Cfg Write

Completion

Spec

Core

Spec

Core

Spec

Core

Spec

Core

Spec

Core

Posted

Memory Write or
Message
Request

N

(1)

Y/N

(2)

N

(1)

N

(2)

yes

yes

yes

yes

Y/N

(1)

Y

(2)

N

(1)

N

(2)

Y/N

(1)

Y

(2)

No

(1)

No

(2)

NonPos

ted

Read Request

No

No

Y/N

Yes

(1)

Y/N

Yes

(2)

Y/N

No

Y/N

No

I/O or
Configuration
Write Request

No

No

Y/N

Yes

(3)

Y/N

Yes

(4)

Y/N

No

Y/N

No