Altera IP Compiler for PCI Express - Manual (Page 254)

15–22 Chapter 15: Testbench and Design Example
Root Port Design Example
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
2. Sets up the chaining DMA descriptor header and starts the transfer data from the
BFM shared memory to the endpoint memory by calling the procedure
dma_set_header
which writes four dwords, DW0:DW3, ( Table 15–21 ) into the
DMA read register module.
After writing the last dword of the Descriptor header (DW3), the DMA read starts
the three subsequent data transfers.
3. Waits for the DMA read completion by polling the BFM share memory location
0x90c, where the DMA read engine is updating the value of the number of
completed descriptors. Calls the procedures rcmem_poll and msi_poll to
determine when the DMA read transfers have completed.
Root Port Design Example
The design example includes the following primary components:
■ IP Compiler for PCI Express root port variation (.v).
■ VC0:1 Avalon-ST Interfaces (altpcietb_bfm_vc_intf_ast)—handles the transfer of
PCI Express requests and completions to and from the IP Compiler for PCI
Express variation using the Avalon-ST interface.
■ Root Port BFM tasks—contains the high-level tasks called by the test driver,
low-level tasks that request PCI Express transfers from altpcietb_bfm_vc_intf_ast,
the root port memory space, and simulation functions such as displaying
messages and stopping simulation.
Table 15–21. DMA Control Register Setup for DMA Read
Offset in DMA Control
Registers (BAR2)
Value Description
DW0 0x0 3
Number of descriptors and control bits as described in Table 15–5 on
page 15–14
DW1 0x14 0 BFM shared memory upper address value
DW2 0x18 0x900 BFM shared memory lower address value
DW3 0x1c 2 Last descriptor written