Altera IP Compiler for PCI Express - Manual (Page 95)

Chapter 5: IP Core Interfaces 5–9
Avalon-ST Interface
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Table 5–3 shows the byte ordering for header and data packets for Figure 5–5 through
Figure 5–13 .
Figure 5–5 illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a
three dword header with non-qword aligned addresses with a 64-bit bus. In this
example, the byte address is unaligned and ends with 0x4, causing the first data to
correspond to rx_st_data[63:32].
f For more information about the Avalon-ST protocol, refer to the Avalon Interface
Specifications.
1
The Avalon-ST protocol, as defined in Avalon Interface Specifications , is big endian, but
the IP Compiler for PCI Express packs symbols into words in little endian format.
Consequently, you cannot use the standard data format adapters that use the Avalon-
ST interface.
Table 5–3. Mapping Avalon-ST Packets to PCI Express TLPs
Packet TLP
Header0 pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3
Header1 pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7
Header2 pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11
Header3 pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15
Data0 pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0
Data1 pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4
Data2 pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8
Data pcie_data_byte, pcie_data_byte, pcie_data_byte-2, pcie_data_byte
Figure 5–5. 64-Bit Avalon-ST rx_st_data Cycle Definition for 3-DWord Header TLPs with Non-QWord Aligned Address
clk
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_be[7:4]
rx_st_be[3:0]
Header1 Data0 Data2
Header0 Header2 Data1
F F
F