NEC PD78214 - Manual (Page 402)

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Chapter 13 Local Bus Interface Function
13
(3) When macro service Type A or Type C is used in external memory expansion mode (the µPD78213 always uses
external memory), an illegal write access may occur.
This occurs when any of the following three conditions is satisfied:
(a) Data is transferred from memory to an SFR using macro service Type A, and the transfer data is D0H to
DFH.
(b) Data is transferred from an SFR to memory by using macro service Type A, and the transfer destination
buffer (memory) address is 0FED0H to 0FEDFH upon execution of the macro service.
(c) The MPTL address is 0FED0H to 0FEDFH when macro service Type C is used.
An illegal write access is performed in the same way as during normal memory access. In addition, wait states
are inserted according to the setting of bits PW20 and PW21 of the memory expansion mode register (MM).
Table 13-3 lists the conditions and operations for illegal write access.
Table 13-3 Conditions and Operations for Illegal Write Access
Condition
Macro service
type
1
2
3
A
A
C
Illegal write access
Data
Data transferred by macro
service
Low-order 8 bits of transfer
destination buffer (memory)
address
Low-order 8 bits of MPTL
address
Address
Transfer destination SFR
address
Transfer destination SFR
(CR10 or CR11) address
Transfer target SFR address
This problem can be avoided by applying the following methods:
1. The problem caused by condition 1 is difficult to avoid by means of software (whether an illegal access
occurs depends on the transfer data). The problem must be avoided by using the external address
decoder so that the area at addresses 0FF00H to 0FFFFH does not overlap the addresses of the external
circuits.
2. When the macro service being used does not satisfy condition 1 (transfer from memory to an SFR is not
performed by macro service Type A), or when condition 2 is satisfied, the buffer area must be mapped
to an address other than addresses 0FED0H to 0FEDFH. In the case of condition 3, the MPTL must be
mapped to an address other than addresses 0FED0H to 0FEDFH.
This problem can also occur in the in-circuit emulator.
(4) When using the external wait signal, set bit 6 of register PM6 to 1 to set pin P66/WAIT to input mode.
(5) If the RFEN bit of the refresh mode register (RFM) is already set to 1 (or is simultaneously set to 1) when the
RFLV bit is changed from 0 to 1, pin REFRQ may output a glitch, having a peak level of approximately 2.6 V,
for approximately 10 ns.
When setting the RFLV bit to 1, follow the steps shown in Fig. 13-24. The 200-ns delay after setting RFEN
assures the access disabled time when pseudo static RAM returns from self-refresh mode.