NEC PD78214 - Manual (Page 110)

81
Chapter 5 Port Functions
5
Fig. 5-28 Port 5 Mode Register Format
Table 5-6 Port 5 Operating Modes
1
1
0
0
1
×
MM2
0
1
×
MM1
Ч
1
Ч
MM0
EA pin
MM register bit
Operation mode
I/O port
Address/data bus
(A8-A15)
For the
µPD78213, port 4 functions only as the address/data bus (AD8 through AD15).
5.6.3 Operation
Port 5 is an I/O port. Its pins also function as control signal pins.
(1) Output port
When port 5 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can
be transferred between the output latch and the accumulator using a transfer instruction. The output latch can
be loaded with any data by a logical operation instruction. Once the output latch is loaded with some data, it retains
the data until it is loaded
Note with other data.
Note This includes a case in which any other bit of the same port is manipulated using a bit manipulation instruction.
Fig. 5-29 Port Specified as an Output Port
(2) Input port
The level of each pin of port 5 can be transferred to the accumulator by a transfer instruction. Also in this case,
data can be written to the output latches, and all output latches store data transferred from the accumulator
by a transfer instruction or other similar instruction, regardless of the current mode of the port operation. If
a bit is specified as an input port, however, the latched data is not output to the port pin because the output
buffer at the pin is in the high-impedance state. (When the pin is switched from the input mode to the output
mode, the contents of the output latch are output to the port pin.) If a bit is specified as an input port, the
contents of the output latch for the pin cannot be transferred to the accumulator.
PM57
7
PM56
6
PM55
5
PM54
4
PM53
3
PM52
2
PM51
1
PM50
0
PM5
PM5n
Input mode (output buffer OFF)
Output mode (output buffer ON)
Specifies I/O mode of pin PM5n (n = 0 to 7)
(FFH when RESET is input)
0
1
P5n
n = 0 to 7
Internal bus
WR
PORT
RD OUT
Output
Iatch