NEC PD78214 - Manual (Page 242)

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Chapter 7 Timer/Counter Units
7
(2) The OVFm flag for holding an overflow from a timer/counter is contained in register TMCn used to control the
operation of the timer/counter. When a read/modify/write instruction (such as AND TMCn,#7FH) is executed,
for example, the OVFm flag may be cleared. (Even if the OVFm flag is 0 when the OVFm flag is read by the
CPU, the OVFm flag may already be set to 1 by a timer/counter overflow when the OVFm flag is rewritten to
by the CPU. However, the OVFm flag was 0 when being read by the CPU, so that the OVFm flag is cleared to
0.)
To prevent the OVFm flag of a timer/counter controlled by register TMCn from being cleared, use the method
below.
1. Read the TMm register of the timer/counter using the OVFm flag.
2. After a timer/counter operation, read the TMm register again.
3. Make a comparison between two read values. Set the OVFm flag if the value read later is smaller than
the value read first.
When this method is used, the OVFm flag must not be manipulated. In addition, the time between the first
TMm read operation and the next TMm read operation must be shorter than the full-count time of TMm.
Example: To prevent the OVF1 flag of timer/counter 1 from being cleared
MOV A,TM1
MOV TMC1,#xxx01000B ; xxx depends on the manipulation of timer/counter 2.
CMP A,TM1 ; Checks the timer value.
BL $NEXT
BE $NEXT
MOV TMC1,#xxx011000B ; Sets OVF1.
NEXT:
(3) If the value of a compare register coincides with the value of a timer register when an instruction for stopping
timer operation is executed, the count operation of the timer stops, but an interrupt request is generated.
To prevent an interrupt request from being generated when timer operation is stopped, mask the interrupt
by using the mask register before stopping the timer.
Program that can generate an interrupt request Program that generates no interrupt request
Example: MOV TMC1, #6CH
AND MK0H, #0F6H
(4) After an operation for starting a timer/counter is performed (CEn ← 1: n = 0 to 3), a maximum of 1 count clock
pulse is required until the timer/counter actually starts. (See Fig. 7-132.)
When a timer/counter is used as an interval timer, for example, the first interval is longer by a maximum of
1 clock pulse. After the first interval, the specified interval occurs.
← An interrupt request
is generated from the
timer/counter be-
tween these instruc-
tions.
← The interrupt request
flag for timer/counter
2 is cleared.
← An interrupt from
timer/counter 2 is disa-
bled.
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AND MK0H, #0F6H
MOV TMC1, #6CH
AND IF0H, #0F6H
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