NEC PD78214 - Manual (Page 151)

122
µ
PD78214 Sub-Series
7.1.7 PWM Output
The PWM output function outputs a PWM signal whose period coincides with the full-count period of 16-bit timer
0 (TM0). The pulse width of TO0 is determined by the value of CR00, and the pulse width of TO1 is determined
by the value of CR01. Before this function can be used, the CLR01 bit of capture/compare control register 0 (CRC0)
must be set to 0.
The pulse period and pulse width are as follows:
• PWM period = 524288/f
CLK
• PWM pulse width = (value set in compare register Note ) × 8 + 2/f
CLK
(value set in compare register) × 8/f
CLK
Note Zero cannot be set in the compare registers.
• Duty factor = (PWM pulse width)/(PWM period) = ((value set in compare register)
Ч 8 + 2)/(65536 Ч 8) (value
set in compare register)/65536
Caution In PWM output, the actual pulse width is longer than a value obtained with the approximate expression by two clock pulses of f
CLK
for the active level, and is shorter than such an approximate value by two clock pulses of f
CLK
for the inactive level. Take this point
into consideration when high-precision output is required.
Fig. 7-13 PWM Pulse Output
Remark ALV0 = 0
Table 7-7 PWM Output on TO0 and TO1 (f
CLK
= 6 MHz)
Count clock
f
CLK
/8
Minimum pulse width
1.3 µs
PWM period
87.4 ms
PWM frequency
11.4 Hz
Fig. 7-14 shows an example of 2-channel PWM output. Fig. 7-15 shows PWM output when FFFFH is set in the CR00
compare register.
FFFFH
TO0
0H
Count value of timer
Count starts
CR00
CR00
CR00
Interrupt
FFFFH FFFFH
Pulse width
Pulse period Pulse period
Pulse width