NEC PD78214 - Manual (Page 282)

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Chapter 9 Asynchronous Serial Interface
9
9.4.3 Operation of the Baud Rate Generator for UART
The baud rate generator for UART starts operating, when the CE bit of the baud rate generator control register
(BRGC) is set to 1. The baud rate clock to be generated is a signal obtained by dividing either the internal system
clock (f
CLK
) or the clock input from the external baud rate input (ASCK) pin.
Resetting the CE bit to 0 stops the operation of the baud rate generator.
When the CE is 1, if an attempt is made to set it to 1 again, the 4-bit counter and frequency divider for baud rate
generation are reset, then baud rate clock generation starts again.
Caution When a BRGC register write instruction is executed, the 4-bit counter and the frequency divider are reset. If the BRGC register is
write-accessed during transmission, the baud rate being generated is disrupted, hampering normal communication. For this
reason, do not write to the BRGC register during transmission.
(1) Generating the baud rate clock from the internal system clock (f
CLK
)
The internal system clock (f
CLK
) is divided by the 4-bit counter. The resultant signal is further divided by the
frequency divider to generate the baud rate clock.
The baud rate generated from the internal system clock (f
CLK
) is determined by the following formula:
(Baud rate) = f
CLK
/(k + 1)
× 1/n × 1/16
where, f
CLK
: Internal system clock frequency
k : Value set in the MDL3 to MDL0 bits of the BRGC register (k = 1 through 14; see Fig. 9-9.)
1/n : Frequency divider tap
16 : Serial data sampling rate
(2) Generating the baud rate clock from the ASCK input
Both edges of an input to the ASCK pin are detected to generate a clock having the frequency two times as
high as the frequency at the ASCK pin. The resultant clock is then divided at the frequency divider. This
function makes it possible to generate more than one baud rate from one external input clock.
The baud rate generated from the input to the ASCK pin is determined by the following formula:
(Baud rate) = f
ASCK
× 2/n × 1/16
where, f
ASCK
: ASCK input clock frequency
Note that the ASCK input cannot be higher than f
CLK
/24 (250 kHz for f
CLK
= 6 MHz).