NEC PD78214 - Manual (Page 280)

251
Chapter 9 Asynchronous Serial Interface
9
9.4 BAUD RATE GENERATOR
9.4.1 Configuration of the Baud Rate Generator for UART
Fig. 9-8 shows the configuration of the baud rate generator.
Fig. 9-8 Baud Rate Generator Clock Configuration
(1) 4-bit counter
The 4-bit counter counts the internal system clock (f
CLK
). It generates a signal having the frequency selected
by the lower four bits of the baud rate generator control register (BRGC).
(2) Frequency divider
The frequency divider divides the signal input from the 4-bit counter or an external baud rate input (ASCK),
and allows the selector at the next stage to select the clock for the baud rate.
(3) Both-edge detector
The both-edge detector detects either edge of the signal input to the ASCK pin and generates a signal having
a frequency two times as high as the ASCK input clock frequency. See Chapter 11 for details of edge detection.
9.4.2 Baud Rate Generator Control Register (BRGC)
The BRGC register is an 8-bit register that holds the clock for baud rate generation controlled according to the
internal system clock (f
CLK
).
Only an 8-bit manipulation instruction can be used for this register, and its use is limited to write operations. Fig.
9-9 shows the format of the register.
When the RESET signal is input, the BRGC register is reset to 00H.
Caution When a BRGC register write instruction is executed, the 4-bit counter and the frequency divider are reset. If the BRGC register is
write-accessed during transmission, the baud rate being generated is disrupted, hampering normal communication. For this
reason, do not write to the BRGC register during transmission.
8
SCK
ASIM BRGC
RESET
Coincidence
4
4
Clear
f CLK
8
1
2
Internal bus
8-bit timer/counter 3 output
Frequency divider
Selector Selector
Selector
INTP4/ASCK
Baud rate generator
control register
4-bit counter
Asynchronous serial
interface
Clock synchronous
serial interface
Resets writing
to BRGC