NEC PD78214 - Manual (Page 196)

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Chapter 7 Timer/Counter Units
7
7.3.4 Operation of 8-Bit Timer 2 (TM2)
(1) Basic operation
Eight-bit timer/counter 2 performs count operation by counting up with the count clock specified by the higher
4 bits of prescaler mode register 1 (PRM1).
Bit 7 (CE2) of timer control register 1 (TMC1) is used to enable/disable count operation. (The higher 4 bits of
the TMC1 register are used to control the operation of 8-bit timer/counter 2.) When the CE2 bit is set to 1 by
software, TM2 is cleared to 00H by the first count clock pulse, then count-up operation starts.
When the CE2 bit is reset to 0 by software, TM2 is cleared to 00H by the next count clock pulse, then capture
operation and coincide with signal generation stop.
If the CE2 bit is set to 1 when the CE2 bit is already set to 1, TM2 count operation is not affected. (See Fig. 7-
71 (b).)
If the count clock signal is applied when the value of TM2 is FFH, TM2 is set to 00H. At this time, OVF2 is set,
and the overflow signal is sent to the output control circuit. OVF2 can be cleared only by software. Count
operation continues.
When the RESET signal is applied, TM2 is cleared to 00H, and count operation stops.
Fig. 7-71 Basic Operation of 8-Bit Timer 2 (TM2)
(a) Count start → count stop → count start
(b) When the CE2 bit is set to 1 again after count operation starts
CE2
TM2
Count starts Count stops
CE2 ←1 CE2 ←0
Count starts
CE2 ←1
0H 1H 2H 0FH 10H 11H 0H 1H 0H 0H
Count clock
Count starts
CE2 ←1 CE2 ←1
Count clock
CE2
TM2
Rewriting
0H 0H 1H 2H 3H 4H 5H 6H