NEC PD78214 - Manual (Page 375)

346
µ
PD78214 Sub-Series
13.1 CONTROL REGISTERS
13.1.1 Memory Expansion Mode Register (MM)
The MM register is an 8-bit register for controlling externally expanded memory, specifying the number of wait
states (address space: 00000H to 0FFFFH), and controlling the internal fetch cycle.
The MM register can be read and written with 8-bit manipulation instructions and bit manipulation instructions.
Fig. 13-1 shows the format of the MM register.
When the RESET signal is applied, the register is set to 20H.
Fig. 13-1 Format of the Memory Expansion Mode Register (MM)
IFCH
7
MM6
6
PW21
5
PW20
4
0
3
MM2
2
MM1
1
MM0
0
MM
MM2
0
0
MM1
0
0
MM0
0
1
PW21
1
0
Number of wait states (range: 00000H to 0FFFFH)
0
0
PW20
0
1
2 1 0
Number of wait states equivalent to low level period of
WAIT pin input
1 1
Mode
Single-chip
mode
P50-P57
Port mode
P40-P47
Input mode
P65
Port mode
Output mode
P65
External
memory
expansion
mode
1 1 1 WR RD A8-A15 AD0-AD7
MM6
Output latch for P60 to P63 (P60 to P63) stores higher address
(A16 to A19) in external memory expansion mode and P60 to P63
function as A16 to A19 output pins.
P60 to P63 as general-purpose output port
Specifies 1M-byte expansion mode
0
1
IFCH
High-speed internal ROM fetch (execution cycle is faster than
that for external ROM fetch)
Instruction execution cycle, the same as the external ROM fetch cycle
Controls internal fetch cycle
0
1