Avago Technologies LSI53C876E User Manual
Avago Technologies Hardware
Table of contents
Document Outline
- Chapter1 General Description
- Chapter2 Functional Description
- Figure2.1 LSI53C876 Block Diagram
- 2.1 PCI Functional Description
- 2.1.1 PCI Addressing
- 2.1.2 PCI Bus Commands and Functions Supported
- Table 2.1 PCI Bus Commands and Encoding Types
- 2.1.2.1 Interrupt Acknowledge Command
- 2.1.2.2 Special Cycle Command
- 2.1.2.3 I/O Read Command
- 2.1.2.4 I/O Write Command
- 2.1.2.5 Reserved Command
- 2.1.2.6 Memory Read Command
- 2.1.2.7 Memory Write Command
- 2.1.2.8 Configuration Read Command
- 2.1.2.9 Configuration Write Command
- 2.1.2.10 Memory Read Multiple Command
- 2.1.2.11 Dual Address Cycles (DACs) Command
- 2.1.2.12 Memory Read Line Command
- 2.1.2.13 Memory Write and Invalidate Command
- 2.1.3 Internal Arbiter
- 2.1.4 PCI Cache Mode
- 2.2 SCSI Functional Description
- 2.2.1 Two SCSI Controllers
- 2.2.2 SCRIPTS Processor
- 2.2.3 JTAG Boundary Scan Testing
- 2.2.4 SCSI Loopback Mode
- 2.2.5 Parity Options
- 2.2.6 DMA FIFO
- 2.2.7 SCSI Bus Interface
- 2.2.8 Synchronous Operation
- 2.2.9 Designing a Wide Ultra SCSI System
- 2.2.10 Interrupt Handling
- 2.2.11 Chained Block Moves
- 2.3 Parallel ROM Interface
- 2.4 Serial EEPROM Interface
- 2.5 Power Management
- Chapter3 Signal Descriptions
- Figure3.1 LSI53C876 208-Pin PQFP Diagram
- Figure3.2 LSI53C876 256-Ball BGA Diagram (Top View)
- Figure3.3 LSI53C876 Functional Signal Grouping
- 3.1 PCI Interface Signals
- 3.2 SCSI Bus Interface Signals
- 3.3 ROM/Flash Interface Signals
- 3.4 Test Interface Signals
- 3.5 Power and Ground Signals
- 3.6 MAD Bus Programming
- Chapter4 Registers
- Chapter5 SCSI SCRIPTS Instruction Set
- Chapter6 Electrical Characteristics
- 6.1 DC Characteristics
- Table 6.1 Absolute Maximum Stress Ratings
- Table 6.2 Operating Conditions
- Table 6.3 SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SACK/
- Table 6.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/
- Table 6.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN, DIFFSENS
- Table 6.6 Capacitance
- Table 6.7 Output Signals—INTA/, INTB/
- Table 6.8 Output Signals—SDIR[15:0], SDIRP0, SDIRP1, BSYDIR, SELDIR, RSTDIR, TGS, IGS, MAS/[1:0],...
- Table 6.9 Output Signal—REQ/
- Table 6.10 Output Signal—SERR/
- Table 6.11 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR...
- Table 6.12 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO2, GPIO3, GPIO4
- Table 6.13 Bidirectional Signals—MAD[7:0]
- Table 6.14 Input Signals—TDI, TMS, TCK
- Table 6.15 Output Signal—TDO
- 6.2 3.3 V PCI DC Characteristics
- 6.3 TolerANT Technology Electrical Characteristics
- 6.4 AC Characteristics
- Table 6.21 Clock Timing
- Figure6.6 Clock Timing
- Table 6.22 Reset Input
- Figure6.7 Reset Input
- Table 6.23 Interrupt Output
- Figure6.8 Interrupt Output
- 6.4.1 PCI and External Memory Interface Timings
- 6.4.1.1 3.3 V PCI Timings
- Table 6.24 3.3 V PCI Timing
- Table 6.25 Configuration Register Read
- Figure6.9 Configuration Register Read
- Table 6.26 Configuration Register Write
- Figure6.10 Configuration Register Write
- Table 6.27 Target Read (Not From External Memory)
- Figure6.11 Target Read (Not From External Memory)
- Table 6.28 Target Write (Not From External Memory)
- Figure6.12 Target Write (Not From External Memory)
- Table 6.29 Target Read (From External Memory)
- Figure6.13 Target Read, from External Memory
- Table 6.30 Target Write (From External Memory)
- Figure6.14 Target Write, from External Memory
- Table 6.31 Opcode Fetch, Nonburst
- Figure6.15 Opcode Fetch, Nonburst
- Table 6.32 Opcode Fetch, Burst
- Figure6.16 Opcode Fetch, Burst
- Table 6.33 Back-to-Back Read
- Figure6.17 Back-to-Back Read
- Table 6.34 Back-to-Back Write
- Figure6.18 Back-to-Back Write
- Table 6.35 Burst Read
- Figure6.19 Burst Read
- Table 6.36 Burst Write
- Figure6.20 Burst Write
- Table 6.37 Read Cycle, Norma/Fast Memory (³ 128 Kbytes), Single Byte Access
- Figure6.21 Read Cycle, Normal/Fast Memory (³ 128 Kbytes), Single Byte Access
- Table 6.38 Write Cycle, Normal/Fast Memory (³ 128 Kbytes), Single Byte Access
- Figure6.22 Write Cycle, Normal/Fast Memory (³ 128 Kbytes), Single Byte Access
- Figure6.23 Read Cycle, Normal/Fast Memory (³ 128 Kbyte), Multiple Byte Access
- Figure6.24 Write Cycle, Normal/Fast Memory (³ 128 Kbyte), Multiple Byte Access
- Table 6.39 Read Cycle, Slow Memory (³ 128 Kbytes)
- Figure6.25 Read Cycle, Slow Memory (³ 128 Kbytes)
- Table 6.40 Write Cycle, Slow Memory (³ 128 Kbytes)
- Figure6.26 Write Cycle, Slow Memory (³ 128 Kbytes)
- Figure6.27 Read Cycle, 16 Kbytes ROM
- Figure6.28 Read Cycle, 16 Kbytes ROM
- Table 6.41 Write Cycle, 16 Kbytes ROM
- Figure6.29 Write Cycle, 16 Kbytes ROM
- 6.4.1.1 3.3 V PCI Timings
- 6.4.2 PCI and External Memory Interface Timing
- 6.4.3 SCSI Interface Timing
- Table 6.43 Initiator Asynchronous Send
- Figure6.30 Initiator Asynchronous Send
- Table 6.44 Initiator Asynchronous Receive
- Figure6.31 Initiator Asynchronous Receive
- Table 6.45 Target Asynchronous Send
- Figure6.32 Target Asynchronous Send
- Table 6.46 Target Asynchronous Receive
- Figure6.33 Target Asynchronous Receive
- Figure6.34 Initiator and Target Synchronous Transfers
- Table 6.47 SCSI-1 Transfers (SE, 5.0 Mbytes/s)
- Table 6.48 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers) or 20.0 Mbytes/s (16-Bit Transf...
- Table 6.49 SCSI-2 Fast-20 SE Transfers (20.0 Mbytes/s (8-Bit Transfers) or 40.0Mbytes/s (16-Bit ...
- 6.5 Package Diagrams
- 6.1 DC Characteristics
- AppendixA Register Summary
- AppendixB External Memory Interface Diagram Examples
- Index
- Customer Feedback