Avago Technologies LSI53C876E - Manual (Page 307)

Index IX-3
E
electrical characteristics
AC characteristics 6-12
DC characteristics
3.3 volt PCI 6-7
TolerANT technology 6-8
enable parity checking 2-17
enable parity checking bit 4-24
enable read line bit 4-68
enable read multiple bit 4-68
enable response to reselection bit 4-32
enable response to selection bit 4-33
enable wide SCSI bit 4-31
encoded chip SCSI ID 4-33
encoded destination SCSI ID bit 4-40
encoded destination SCSI ID bits 4-36
EPROMs 1-1
error recording signals 3-9
even parity 2-17
expanded register move 1-6
expansion ROM base address 4-13
expansion ROM base address register 2-45
extend SREQ/SACK filtering bit 4-91
external memory configurations 6-15
external memory interface 2-44
configuration 2-44
GPIO4 bit 4-37
slow memory 2-45
extra clock cycle of data setup bit 4-25
F
fetch enable 4-82
fetch pin mode bit 4-57
FIFO byte control bits 4-60
FIFO flags bits 4-46
,
4-49
flush DMA FIFO bit 4-56
FRAME/ 3-8
function complete 2-35
function complete bit 4-73
,
4-77
G
general purpose I/O pin 0 3-11
,
3-12
general purpose I/O pin 1 3-11
,
3-12
general purpose I/O pin 2 3-11
general purpose I/O pin 3 3-11
,
3-12
general purpose I/O pin 4 3-11
,
3-12
general purpose pin control register 4-82
general purpose register 4-37
general purpose timer expired bit 4-76
,
4-79
general purpose timer period bits 4-85
general purpose timer scale factor bit 4-85
GNT/ 3-9
GPCNTL register 4-82
GPI00_ FETCH/ 3-11
,
3-12
GPIO enable bit 4-83
GPIO interface signals 3-11
GPIO[4:0] bits 4-37
GPIO1_ MASTER/ 3-11
,
3-12
GPIO2 3-11
,
3-12
GPIO3 3-11
,
3-12
GPIO4 3-11
,
3-12
GPREG register 4-37
grant 3-9
H
halt SCSI clock bit 4-93
handshake-to-handshake timer bus activity enable bit 4-85
handshake-to-handshake timer expired bit 4-76
,
4-79
handshake-to-handshake timer period bit 4-83
hardware interrupts 2-33
header type (HT[7:0]) 4-8
high impedance mode bit 4-59
I
I/O instructions 5-13
I/O read command 2-5
I/O space 2-3
,
2-4
I/O write command 2-5
IDSEL 2-3
,
3-8
IDSEL signal 2-6
IGS 3-16
,
3-17
illegal instruction detected bit 4-43
immediate arbitration bit 4-26
initialization device select 3-8
initiator ready 3-8
input 3-5
instruction prefetching 2-14
prefetch enable bit 4-70
prefetch flush bit 4-70
prefetch unit flushing 2-15
instructions
block move 5-6
I/O 5-13
load and store 5-38
memory move 5-34
read/write 5-22
transfer control 5-27
INTA routing enable 3-21
INTA/ 2-33
,
3-10
,
3-21
INTA/ pin 2-36
,
2-39
INTB/ 3-10
,
3-21
integration 1-7
interface control pins 3-8
internal arbiter 2-10
internal RAM, see also SCRIPTS RAM 2-14
internal SCRIPTS RAM 2-14
interrupt
line 4-14
pin (IP[7:0]) 4-15
interrupt A 3-10
interrupt B 3-10
interrupt request 2-33
interrupt status register 4-50
interrupt-on-the-fly bit 4-52
interrupts 2-33
,
2-35
fatal vs. nonfatal interrupts 2-35
halting 2-38
IRQ disable bit 2-35
masking 2-36
sample interrupt service routine 2-39
stacked interrupts 2-37
IRDY/ 3-8
IRQ disable bit 4-71
ISTAT 2-34
ISTAT register 4-50