Avago Technologies LSI53C876E - Manual (Page 141)

SCSI Registers 4-47
SDP0L Latched SCSI Parity 3
This bit reflects the SCSI parity signal (SDP0/),
corresponding to the data latched in the
SCSI Input Data
Latch (SIDL) register. It changes when a new byte is
latched into the least significant byte of the SIDL register.
This bit is active HIGH, in other words, it is set when the
parity signal is active.
MSG SCSI MSG/ Signal 2
C_D SCSI C_D/ Signal 1
I_O SCSI I_O/ Signal 0
These three SCSI phase status bits (MSG, C_D, and
I_O) are latched on the asserting edge of SREQ/ when
operating in either initiator or target mode. These bits are
set when the corresponding signal is active. They are
useful when operating in low level mode.
0 1 0 1 0 10
0 1 0 1 1 11
0 1 1 0 0 12
0 1 1 0 1 13
0 1 1 1 0 14
0 1 1 1 1 15
1 0 0 0 0 16
Table 4.6 SCSI Synchronous Data FIFO Word
Count (Cont.)
FF4
(SSTAT2 bit 4) FF3 FF2 FF1 FF0
Bytes or
Words in
the SCSI
FIFO