Avago Technologies LSI53C876E - Manual (Page 306)

IX-2 Index
cache line size enable bit 4-70
cache mode, see PCI cache mode 2-11
cap_ID (CID[7:0]) 4-16
capabilities pointer (CP[7:0]) 4-14
chained block move SCRIPTS instruction 2-42
chained block moves 2-40
SODL register 2-42
SWIDE register 2-41
wide SCSI receive bit 2-41
wide SCSI send bit 2-41
chained mode bit 4-28
chip revision level bits 4-56
chip test five register 4-61
chip test four register 4-59
chip test one register 4-54
chip test six register 4-62
chip test two register 4-54
chip test zero register 4-53
chip type bits 4-82
CHMOV 2-40
clear DMA FIFO 2-38
clear DMA FIFO bit 4-56
clear SCSI FIFO bit 4-93
CLF 2-38
CLK 3-6
clock 3-6
clock address incrementor bit 4-61
clock byte counter bit 4-61
clock conversion factor 2-31
clock conversion factor bits 4-32
CLSE 2-7
,
2-8
CMP 2-35
configuration read command 2-6
configuration registers
base address one (memory) 4-10
base address two (memory) 4-10
base address zero (I/O) 4-9
BIST 4-9
cache line size 4-7
capabilities pointer 4-14
capability ID 4-16
class code 4-7
command 4-3
data 4-20
device ID 4-3
expansion ROM base address 4-13
header type 4-8
interrupt line 4-14
interrupt pin 4-15
latency timer 4-8
max_lat 4-16
min_gnt 4-15
next item pointer 4-17
power management capabilities 4-17
power management control/status 4-17
,
4-18
revision ID 4-7
status 4-5
subsystem ID 4-12
subsystem vendor ID 4-11
vendor ID 4-3
configuration space 2-3
configuration write command 2-6
configured as I/O bit 4-55
configured as memory bit 4-55
connected bit 4-26
,
4-51
conventions 1-7
CSF 2-38
CTEST0 register 4-53
CTEST1 register 4-54
CTEST2 register 4-54
CTEST4 register 4-59
CTEST5 register 4-61
CTEST6 register 4-62
cycle frame 3-8
D
data
(DATA[7:0]) 4-20
data acknowledge status bit 4-56
data path 2-21
data request status bit 4-55
data structure address register 4-49
data transfer direction bit 4-54
data-in 2-42
,
2-43
data-out 2-42
,
2-43
DBC register 4-63
DCMD register 4-64
DCNTL 2-35
DCNTL register 4-70
designing a wide Ultra SCSI system 2-32
destination I/O-memory enable bit 4-67
determining the data transfer rate 2-30
device select 3-8
DEVSEL/ 3-8
DFIFO register 4-58
DIEN 2-35
,
2-36
DIEN register 4-69
differential mode
operation 2-24
DIFFSENS 3-16
,
3-17
DIFFSENS SCSI signal 6-3
DIP 2-34
,
2-37
,
2-38
,
2-39
disable halt on parity error or ATN 4-25
disable single initiator response bit 4-93
DMA byte counter register 4-63
DMA command register 4-64
DMA control register 4-70
DMA core 1-3
DMA direction bit 4-61
DMA FIFO 2-9
,
2-20
,
2-34
DMA FIFO bits 4-62
DMA FIFO empty bit 4-42
DMA FIFO register 4-58
DMA interrupt enable register 4-69
DMA interrupt pending bit 4-53
DMA interrupts 2-35
,
2-36
,
2-38
DMA mode register 4-66
DMA next address register 4-64
DMA SCRIPTS pointer register 4-64
DMA SCRIPTS pointer save register 4-65
DMA status register 4-42
DMODE register 4-66
DNAD register 4-64
DSA register 4-49
DSP register 4-64
DSPS register 4-65
DSTAT 2-34
DSTAT register 4-42
dual address cycles command 2-7