Avago Technologies LSI53C876E - Manual (Page 184)

4-90 Registers
Register: 0x4E
SCSI Test Two (STEST2)
Read/Write
SCE SCSI Control Enable 7
Setting this bit allows assertion of all SCSI control and
data lines through the
SCSI Output Control Latch (SOCL)
and SCSI Output Data Latch (SODL) registers regardless
of whether the LSI53C876 SCSI function is configured as
a target or initiator.
Note: Do not set this bit during normal operation, since it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
ROF Reset SCSI Offset 6
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. Set this bit if a SCSI gross error
condition occurs and to clear the offset when a
synchronous transfer does not complete successfully.
The bit automatically clears itself after resetting the
synchronous offset.
DIF Differential Mode 5
Setting this bit allows the LSI53C876 SCSI function to
interface to external differential transceivers. Its only real
effect is to 3-state the SBSY/, SSEL/, and SRST/ pads
for use as pure inputs. Clearing this bit enables SE
operation. Set this bit in the initialization routine if the
differential pair interface is used.
SLB SCSI Loopback Mode 4
Setting this bit allows the LSI53C876 SCSI function to
perform SCSI loopback diagnostics. That is, it enables
the SCSI core to simultaneously perform as both the
initiator and the target.
7 6 5 4 3 2 1 0
SCE ROF DIF SLB SZM AWS EXT LOW
0 0 0 0 0 0 0 0