Avago Technologies LSI53C876E - Manual (Page 308)

IX-4 Index
J
JTAG boundary scan testing 2-16
L
last disconnect bit 4-49
latched SCSI parity bit 4-47
latched SCSI parity for SD[15:8] bit 4-49
latency 2-10
timer (LT[7:0]) 4-8
load and store instructions 5-38
no flush option 5-39
prefetch unit and store instructions 2-15
,
5-39
load and store SCRIPTS 1-6
load/store instructions 2-16
lost arbitration bit 4-45
LSI53C700 family compatibility bit 4-72
LSI53C876 benefits 1-5
M
MACNTL register 4-82
MAD bus 2-44
MAD bus programming 3-21
MAD[3:1] 3-22
MAD pins 2-44
MAD[7:0] pins 3-21
manual start mode bit 4-68
MAS0/ 3-18
MAS1/ 3-18
masking 2-36
master control for set or reset pulses bit 4-61
master data parity error bit 4-42
,
4-69
master enable bit 4-82
master parity error enable bit 4-60
max SCSI synchronous offset bits 4-35
max_lat (ML[7:0]) 4-16
MCE/ 3-19
memory access control register 4-82
memory address strobe 0 3-18
memory address strobe 1 3-18
memory address/data bus 3-18
memory chip enable 3-19
memory move instruction 2-12
memory move instructions 5-34
and SCRIPTS instruction prefetching 2-15
no flush option 2-15
memory move misalignment 2-12
memory output enable 3-19
memory read command 2-6
memory read line command 2-7
memory read multiple command 2-6
memory space 2-3
,
2-4
memory write and invalidate command 2-9
memory write command 2-6
memory write enable 3-19
min_gnt (MG[7:0]) 4-15
MOE_TESTOUT 3-19
multiple cache line transfers 2-9
multithreaded I/O 1-6
MWE/ 3-19
N
next_item_ptr (NIP[7:0]) 4-17
no flush memory move instruction 5-35
O
objectives of DMA architecture 2-43
opcode fetch burst capability 2-15
opcode fetch bursting 2-15
operating registers
adder sum output 4-72
chip test five 4-61
chip test four 4-59
chip test one 4-54
chip test six 4-62
chip test three 4-56
chip test two 4-54
chip test zero 4-53
data structure address 4-49
DMA byte counter 4-63
DMA command 4-64
DMA control 4-70
DMA FIFO 4-58
DMA interrupt enable 4-69
DMA mode 4-66
DMA next address 4-64
DMA SCRIPTS pointer 4-64
DMA SCRIPTS pointer save 4-65
DMA status 4-42
general purpose 4-37
general purpose pin control 4-82
interrupt status 4-50
memory access control 4-82
response ID one 4-86
response ID zero 4-86
scratch register A 4-66
scratch register B 4-96
SCSI bus control lines 4-41
SCSI bus data lines 4-95
SCSI chip ID 4-32
SCSI control one register 4-25
SCSI control register two 4-28
SCSI control three 4-31
SCSI control zero 4-22
SCSI destination ID 4-36
SCSI first byte received 4-38
SCSI input data latch 4-94
SCSI interrupt enable one 4-75
SCSI interrupt enable zero 4-73
SCSI interrupt status one 4-79
SCSI interrupt status zero 4-76
SCSI longitudinal parity 4-80
SCSI output control latch 4-39
SCSI output data latch 4-95
SCSI selector ID 4-40
SCSI status one 4-46
SCSI status two 4-48
SCSI status zero 4-44
SCSI test one 4-88
SCSI test three 4-92
SCSI test two 4-90
SCSI test zero 4-87
SCSI timer one 4-85
SCSI timer zero 4-83
SCSI transfer 4-33