Avago Technologies LSI53C876E - Manual (Page 110)

4-16 Registers
Register: 0x3F
Max_Lat
Read Only
ML Max_Lat [7:0]
This register indicates the desired settings for latency
timer values. Max_Lat specifies how often the device
needs to gain access to the PCI bus. The value specified
in these registers is in units of 0.25 microseconds. The
LSI53C876 SCSI function sets this register to 0x40.
Register: 0x40
Capability ID
Read Only
CID Cap_ID [7:0]
This register indicates the type of the current data
structure. This register applies to the LSI53C876E only,
which sets this register to a value of 0x01, indicating the
Power Management Data Structure.
7 0
ML
0 1 0 0 0 0 0 0
7 0
CID
0 0 0 0 0 0 0 1