Avago Technologies LSI53C876E - Manual (Page 93)

MAD Bus Programming 3-21
3.5.1 Isolated Power Supplies
The I/O driver pad rows and digital core have isolated power supplies as
delineated by the "I/O" and "CORE" extensions on their respective V
SS
and V
DD
names.
These power and ground pins should be connected directly to the
primary power and ground planes of the circuit board. Bypass capacitors
of 0.01
µ
F should be applied between adjacent V
SS
and V
DD
pairs
wherever possible. Do not connect bypass capacitors between V
SS
and
V
DD
pairs that cross power and ground bus boundaries.
3.6 MAD Bus Programming
The MAD[7:0] pins, in addition to serving as the address/data bus for the
local memory interface, also are used to program power-up options for
the chip. A particular option is programmed by connecting a 4.7 k
Ω
resistor between the appropriate MAD(x) pin and V
SS
. The pull-down
resistors require that HC or HCT external components are used for the
memory interface.
•
MAD[7] – Serial EEPROM programmable option. Please refer to
Section 2.4, “Serial EEPROM Interface,” in Chapter 2, “Functional
Description,” for details.
•
MAD[6] – Serial EEPROM programmable option. Please refer to
Section 2.4, “Serial EEPROM Interface,” in Chapter 2, “Functional
Description,” for details.
•
MAD[5] – SCRIPTS RAM disable.
•
MAD[4] – INTA/ routing enable. Placing a pull-down resistor on this
pin causes SCSI Function B interrupt requests to appear on the
INTA/ pin, along with SCSI Function A interrupt requests, instead of
on INTB/. Placing a pull-down resistor on this pin also causes the
SCSI Function B interrupt pin register (0x3D) in PCI configuration
space to be programmed to 0x01 instead of 0x02.
•
MAD[3:1] – Used to set the size of the external expansion ROM
device attached. Encoding for these pins are listed in the following
table (“0” indicates a pull-down resistor is attached, “1” indicates no
pull-down resistor attached).