4 masking, Section 2.2.10.4, “masking – Avago Technologies LSI53C876E User Manual
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Functional Description
When operating in Target mode CMP, SEL, RSL, Target mode: SATN/
active (M/A), GEN, and HTH are nonfatal. Refer to the description for the
Disable Halt on a Parity Error or SATN/ active (Target Mode Only) (DHP)
bit in the
register to configure the chip’s
behavior when the SATN/ interrupt is enabled during Target mode
operation. The Interrupt-on-the-Fly interrupt is also nonfatal, since
SCRIPTS can continue when it occurs.
The reason for nonfatal interrupts is to prevent SCRIPTS from stopping
when an interrupt occurs that does not require service from the CPU.
This prevents an interrupt when arbitration is complete (CMP set), when
the LSI53C876 is selected or reselected (SEL or RSL set), when the
initiator asserts ATN (target mode: SATN/ active), or when the General
Purpose or Handshake-to-Handshake timers expire. These interrupts are
not needed for events that occur during high-level SCRIPTS operation.
2.2.10.4 Masking
Masking an interrupt means disabling or ignoring that interrupt. Interrupts
can be masked by clearing bits in the
and
SCSI Interrupt Enable One (SIEN1)
(for SCSI interrupts)
registers or DIEN (for DMA interrupts) register. How the chip responds
to masked interrupts depends on: whether polling or hardware interrupts
are being used; whether the interrupt is fatal or nonfatal; and whether the
chip is operating in the Initiator or Target mode.
If a nonfatal interrupt is masked and that condition occurs, the SCRIPTS
do not stop, the appropriate bit in the
SCSI Interrupt Status Zero (SIST0)
or
SCSI Interrupt Status One (SIST1)
is still set, the SIP bit in the ISTAT
is not set, and the INTA/ (or INTB/) pin is not asserted. See
2.2.10.3, “Fatal vs. Nonfatal Interrupts,”
for a list of the nonfatal interrupts.
If a fatal interrupt is masked and that condition occurs, then the SCRIPTS
still stop, the appropriate bit in the
,
, or
SCSI Interrupt Status One (SIST1)
register is
set, and the SIP or DIP bits in the ISTAT is set, but the INTA/ (or INTB/)
pin is not asserted.