Avago Technologies LSI53C876E User Manual
Page 154
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Registers
MPEE
Master Parity Error Enable
3
Setting this bit enables parity checking during master
data phases. A parity error during a bus master read is
detected by the LSI53C876 SCSI function. A parity error
during a bus master write is detected by the target, and
the LSI53C876 SCSI function is informed of the error by
the PERR/ pin being asserted by the target. When this bit
is cleared, the LSI53C876 SCSI function does not
interrupt if a master parity error occurs. This bit is cleared
at power-up.
FBL[2:0]
FIFO Byte Control
[2:0]
These bits steer the contents of the
register to the appropriate byte lane of the
32-bit DMA FIFO. If the FBL2 bit is set, then FBL1 and
FBL0 determine which of four byte lanes can be read or
written. When cleared, the byte lane which is read or
written is determined by the current contents of the
and
registers. Each of the four bytes that make up the 32-bit
DMA FIFO is accessed by writing these bits to the proper
value. For normal operation, FBL2 must equal zero.
FBL2
FBL1
FBL0
DMA FIFO
Byte Lane
Pins
0
x
x
Disabled
N/A
1
0
0
0
D[7:0]
1
0
1
1
D[15:8]
1
1
0
2
D[23:16]
1
1
1
3
D[31:24]